Single-chip data processing apparatus incorporating an electrically rewritable nonvolatile memory and method of operating the same

A microcontroller comprising:

• a central processing unit (CPU) connected to a plurality of buses;
• a system clock input in signal communication with said CPU for receiving a system clock signal;
• a mode controller in signal communication with the CPU for generating mode control signals to set operational modes of said microcontroller in response to a mode selection signal;
• a bussed communication interface connected to said plurality of buses for interfacing devices external to the microcontroller;
• a memory device in signal communication with the CPU for storing data and control program, said memory device being the only memory in the microcontroller and consisting essentially of an electrically rewritable nonvolatile memory (NVM);
• a program/erase timing controller to keep said NVM synchronized at a constant program/erase speed independent of said system clock signal;
• and
• a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said unbussed serial interface in a first programming mode for receiving an NVM command and at least one of address and data through either one of said bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively, in response to the mode control signals.

A microcontroller comprising:

• a central processing unit (CPU) connected to a plurality of buses;
• a system clock input in signal communication with said CPU for receiving a system clock signal;
• a mode controller for generating mode control signals to set operation modes of said microcontroller in response to a mode selection signal;
• a bussed communication interface connected to said plurality of buses for interfacing devices external to the microcontroller;
• an electrically rewritable nonvolatile memory (NVM) being the only memory in the microcontroller for storing data and control program;
• a program/erase timing controller to keep said NVM synchronized at a constant program/erase speed independent of said system clock signal;
• and
• a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said unbussed serial interface in a first programming mode for receiving an NVM command and at least one of address and data through either one of said bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively in response to the mode control signals wherein during one mode of operation, the memory controller directly reads from and writes to the NVM with said data and address without intervention from the CPU.

A microcontroller comprising:

• a central processing unit (CPU) connected to a plurality of buses;
• a system clock input in signal communication with said CPU for receiving a system clock signal;
• a mode controller in signal communication with the CPU for generating mode control signals to set operational modes of said microcontroller in response to a mode selection signal;
• a bussed communication interface connected to said plurality of buses for interfacing devices external to the microcontroller;
• an electrically rewritable nonvolatile memory (NVM), being the only memory in the microcontroller, for storing data and control program;
• a program/erase timing controller to keep said NVM synchronized at a constant program/erase speed independent of said system clock signal;
• and
• a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said unbussed serial interface in a first programming mode for receiving an NVM command and at least one of address and data through either one of said bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively, in response to the mode control signals, wherein during one mode of operation, the memory controller halts the CPU and directly reads from and writes to the NVM with said data and address.

A microcontroller comprising:

• a plurality of buses;
• a central processing unit (CPU) connected to said plurality of buses;
• a mode controller in signal communication with said CPU for generating mode control signals to set operational modes of said microcontroller in response to a mode selection command;
• at least one bussed communication interface selectively connected to said plurality of buses;
• an electrically rewritable nonvolatile memory (NVM), being the only memory in the microcontroller, for storing data and control program;
• and
• a memory controller connected to said NVM, including an unbussed serial interface, operatively coupling to either one of said plurality of buses in a second programming mode or to said at least one communication unbussed serial interface and in a first programming mode for receiving an NVM command and at least one of address and data through either one of said at least one bussed communication interface in the second programming mode and said unbussed serial interface in the first programming mode, respectively, in response to the mode control signals;
• wherein said CPU is halted and remains in an inactive state during an update operation of said NVM, thereby reducing the power consumption of said CPU.