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US 6,839,266 B1Granted
Memory module with offset data lines and bit line swizzle configuration
AssigneeRambus Inc.
InventorsBilly Wayne Garrett, Jr., Frederick Abbott Ware, Craig E. Hampel, Richard M. Barth, Don Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J. Sheffler, Ely K. Tsern, Steven Cameron Woo
Life of this patent
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Abstract
A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.
Claims12
A memory module comprising:
- an array of N memory devices, each memory device having M data pins, where N is greater than M, M is equal to or greater than three, and M and N are positive integers;
- and
- N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.
A memory module comprising:
- an array of N memory devices, each memory device having M data pins, where N is greater than M, M is equal to or greater than four, and M and N are positive integers;
- and
- N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.
A memory system, comprising:
- a memory controller;
- a memory module coupled to the memory controller and responsive to memory access commands from the memory controller, the memory module including an array of N memory devices, each memory device having M data pins, where N is greater than M, M is equal to or greater than four, and M and N are positive integers;
- and
- N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.
1 more element
Dependencies are inferred from the claim text.