Method and device for automatically allocating detector addresses in an alarm system
AssigneeJob Lizenz GmbH & Co. KG
InventorGerhard Röpke
Life of this patent
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Abstract
A process for automatically assigning detector addresses in a danger detection system, comprising a master station and at least one two-wire detection line linked thereto to which a multiplicity of detectors are connected wherein each detector has a capacitor for power accumulation, a measuring resistor in one wire, an evaluation device evaluating the voltage drop on the measuring resistor to which an address latch is connected, and a switch controllable by the evaluation device between the wires.
Claims10
A process for automatically assigning detector addresses in a danger detection system, comprising a master station and at least one two-wire detection line linked thereto to which a multiplicity of detectors are connected wherein each detector has a capacitor for power accumulation, a measuring resistor in one wire, an evaluation device evaluating the voltage drop on the measuring resistor to which an address latch is connected, and a switch controllable by the evaluation device between the wires, including the following process steps:
- In a first phase, a voltage is applied to the line from the master station and the capacitors are charged,
- in a second phase, the master station emits a switch signal to close the switches of all detectors on the detection line,
- in a third phase, two constant currents having different levels are impressed on the detection line at a predetermined alternation and are transformed by means of a pulse receiver in the detector into a digital signal constituting a data word which is stored in the address latch, and a logic circuit blocks another information from being rolled into the address latch and opens the switch, and
- the third phase is repeated with another data word for each detector ready for reception the address latch of which is not occupied.
A circuitry for automatically assigning detector addresses in a danger detection system, comprising:
- a master station (Z) which has a power supply (NT), a microprocessor (μC), a constant-current source (K), and a current modulator (M),
- a multiplicity of detectors (M1, M2 . . . Mn) which are connected to at least one two-wire detection line (A, B) wherein
- each detector (M1, M2 . . . Mn) has a capacitor (C1, C2 . . . Cn) connected between the wires (A, B) in series with a diode (D1, D2 . . . Dn), a controllable switch (SK1, SK2 . . . SKn) between the wires (A, B), a measuring resistor (Rm1, Rm2 . . . Rmn), a pulse receiver (PE) disposed on the measuring resistor, a logic circuit (L), and an address latch (SP) connected to the logic circuit (L), and wherein
- the logic circuit (L) is designed so as to close the switch (SK1, SK2 . . . SKn) during a first pulse sequence arriving from the pulse receiver (PE), and inputs it into the address latch (SP) if this one is not occupied yet by an address, during a second pulse sequence arriving from the pulse receiver (PE).
A circuitry for automatically assigning detector addresses in a danger detection system, comprising:
- a master station (Z) which has a power supply (NT), a microprocessor (μC), a constant-current source (K), and a current modulator (M),
- a multiplicity of detectors (M1, M2 . . . Mn) which are connected to at least one two-wire detection line (A, B) wherein
- each detector (M1, M2 . . . Mn) has a capacitor (C1, C2 . . . Cn) connected between the wires (A, B) in series with a diode (D1, D2 . . . Dn), a controllable switch (SK1, SK2 . . . SKn) between the wires (A, B), a measuring resistor (Rm1, Rm2 . . . Rmn), a pulse receiver (PE) connected parallel to the measuring resistor, a logic circuit (L), and an address latch (SP) connected to the logic circuit (L), and wherein
- the logic circuit (L) is designed so as to close the switch (SK1, SK2 . . . SKn) during a first pulse sequence arriving from the pulse receiver (PE), and inputs it into the address latch (SP) if this one is not occupied yet by an address, during a second pulse sequence arriving from the pulse receiver (PE).
Dependencies are inferred from the claim text.