Automatic synthesis script generation for synopsys design compiler

An apparatus for generating synthesis script to synthesize an integrated circuit (IC) design from a RTL code description into a gate-level description, comprising:

• a processor;
• memory connected to said processor;
• said memory having instructions for said processor to:
• cause a logic synthesis tool to generate a generic netlist from the RTL code description;
• identify hardware elements in the generic netlist;
• determine key pins for each of said identified hardware elements;
• extract design structure and design hierarchy from the generic netlist based on the key pins and the identified hardware elements;
• and
• generate script to cause the logic synthesis tool to synthesize the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,
• wherein said script includes instructions to cause the logic synthesis tool to:
• apply bottom-up synthesis to modules and sub-modules of the design,
• apply top-down characterization to modules and sub-modules of the IC design,
• repeat said bottom-up synthesis and said top-down characterization until constraints are satisfied.

An apparatus for generating synthesis script to synthesize an integrated circuit (IC) design from a RTL code description into a gate-level description, comprising:

• means for causing a logic synthesis tool to generate a generic netlist from the RTL code description;
• means for identifying hardware elements in the generic netlist;
• means for
• determining key pins for each of said identified hardware elements;
• means for extracting design structure and design hierarchy from the generic netlist based on the key pins and the identified hardware elements;
• and
• means for generating script to cause the logic synthesis tool to synthesize the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,
• wherein said script includes instructions to cause the logic synthesis tool to:
• apply bottom-up synthesis to modules and sub-modules of the IC design,
• apply top-down characterization to modules and sub-modules of the IC design, and
• repeat said bottom-up synthesis and said top-down characterization until constraints are satisfied.

A computer storage medium containing instructions for generating synthesis script to synthesize an integrated circuit (IC) design from a generic netlist into a gate-level description, said instructions comprising the steps of:

• causing a logic synthesis tool to generate a generic netlist from the RTL code description;
• identifying hardware elements in the generic netlist;
• determining key pins for each of said identified hardware elements;
• extracting design structure and design hierarchy from the generic netlist based on the key pins and the identified hardware elements;
• and
• generating script to cause the logic synthesis tool to synthesize the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,
• wherein said script includes instructions to cause the logic synthesis tool to:
• apply bottom-up synthesis to modules and sub-modules of the IC design,
• apply top-down characterization to modules and sub-modules of the IC design, and
• repeat said bottom-up synthesis and said top-down characterization until constraints are satisfied.

A process for synthesizing an integrated circuit (IC) design from a RTL code description into a gate-level description, said process comprising the steps of:

• generating a generic netlist from the RTL code description;
• identifying hardware elements in the generic netlist;
• determining key pins for the identified hardware elements in the generic netlist;
• extracting design structure and design hierarchy from the generic netlist based on the identified hardware elements and the key pins;
• synthesizing the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,
• wherein said synthesis of the IC design includes:
• applying bottom-up synthesis to modules and sub-modules of the IC design,
• applying top-down characterization to modules and sub-modules of the IC design, and
• repeating said bottom-up synthesis and said top-down characterization until constraints are satisfied.

A computer system for synthesizing an integrated circuit (IC) design from a RTL code description into a gate-level description, said system comprising:

• means for generating a generic netlist from the RTL code description;
• means for identifying hardware elements in the generic netlist;
• means for determining key pins for the identified hardware elements in the generic netlist;
• means for extracting design structure and design hierarchy from the generic netlist based on the identified hardware elements and the key pins;
• means for synthesizing the IC design into a gate-level description based on the design structure and the design hierarchy extracted from the generic netlist,
• wherein said synthesis of the IC design includes:
• applying bottom-up synthesis to modules and sub-modules of the IC design,
• applying top-down characterization to modules and sub-modules of the IC design, and
• repeating said bottom-up synthesis and said top-down characterization until constraints are satisfied.