US 6,836,808 B2Granted

Pipelined packet processing

AssigneeInternational Business Machines Corporation

InventorsRobert Michael Bunce, Christos John Georgiou, Valentina Salapura

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Abstract

A method and system for increasing the efficiency of packet processing within a packet protocol handler. In accordance with the method of the present invention packet processing tasks are performed on multiple processors or threads concurrently and in a pipelined fashion. Subsequent protocol packet processing tasks for processing a single packet are performed on multiple processors or threads, acting as stages of a pipeline. The assignment of tasks to processors or threads is performed dynamically, by checking the availability of a processor or thread in the subsequent pipeline stage. The availability determination includes determining the available capacity of the input work queue associated with each processor or thread. If the subsequent pipeline stage is overloaded, the task is assigned to another processor or thread that is not overloaded.

Claims14

Dependent claims

A method for pipelining processing of a packet within a packet protocol handler, wherein inbound packet processing is performed within said packet protocol handler utilizing an inbound direct memory access (DMA) controller, said method comprising:

performing a packet processing task with respect to a packet in a first processor said performing a packet processing task comprising initiating a first processing thread within said first processor, wherein said first processing thread obtains a memory address for said packet and sets up an inbound DMA for said received packet utilizing said inbound DMA controller, and
performing subsequent packet processing tasks with respect to said packet utilizing subsequent processors or threads, wherein said subsequent processors or threads are dynamically allocated by;
utilizing said inbound DMA controller to move said packet from an inbound buffer into a memory location in accordance with said inbound DMA set up;
responsive to moving the header of said packet, issuing a header received synchronization signal from said inbound DMA controller to said available subsequent processor;
and
responsive to receiving said header received synchronization signal, initiating a second processing thread within said subsequent available processor, wherein said second processing thread reads the packet header and fetches a control block in accordance with packet header information and processes said packet in accordance with said fetched control block.

3 more elements

A system for pipelining processing of a packet within a packet protocol handler, wherein inbound packet processing is performed within said packet protocol handler utilizing an inbound direct memory access (DMA) controller, said system comprising:

processing means for performing a packet processing task with respect to a packet in a first processor, said processing means for performing a packet processing task comprising processing means for initiating a first processing thread within said first processor, wherein said first processing thread obtains a memory address for said packet and sets un an inbound DMA for said received packet utilizing said inbound DMA controller;
and
processing means for performing subsequent packet processing tasks with respect to said packet utilizing subsequent processors or threads, wherein said subsequent processors or threads are dynamically allocated by;
processing means within said inbound DMA controller for moving said packet from an inbound buffer into a memory location in accordance with said inbound DMA set up;
processing means responsive to moving the header of said packet for issuing a header received synchronization signal from said inbound DMA controller to said available subsequent processor;
and
processing means responsive to receiving said header received synchronization signal for initiating a second processing thread within said subsequent available processor, wherein said second processing thread reads the packet header and fetches a control block in accordance with packet header information and processes said packet in accordance with said fetched control block.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/683,863Filed 25 Feb 2002
Published: US 2003/0163589 A128 Aug 2003
Granted: 28 Dec 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

H04L 49/1546
Non-blocking multistage, e.g. Clos: using pipelined operation
H04L 49/90
Packet switching elements: buffering arrangements
H04L 49/103
Characterised by the switching fabric construction: using a shared central buffer; using a shared memory
H04L 49/3018
Peripheral units, e.g. input or output ports: input queuing