Back to results
US 6,834,008 B2Granted
Cross point memory array using multiple modes of operation
AssigneeUnity Semiconductor Corporation
InventorsDarrell Rinerson, Christophe J. Chevallier, Steven W. Longcor, Edmond R. Ward, Wayne Kinney, Steve Kuo-Ren Hsia
Life of this patent
Estimating the term…
Abstract
Cross point memory array using multiple modes of operation. The invention is a cross point memory array that uses a read mode to determine the resistive state of a memory plug, a first write mode to cause the memory plug to change from a first resistive state to a second resistive state, and a second write mode to cause the memory plug to change from the second resistive state back to the first resistive state.
Claims17
A cross point memory array comprising:
- a first layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with each other;
- a second layer of conductive array lines, the conductive array lines being arranged so that they do not come into direct contact with either each other or any of the conductive array lines of the first layer;
- and
- a plurality of memory plugs, each memory plug
- having a memory element that
- in a first write mode, switches from a first resistance state to a second resistance state upon application of a first write voltage pulse across the memory element;
- in a second write mode, reversibly switches from the second resistance state back to the first resistance state upon application of a second write voltage pulse across the memory element;
- and
- in a read mode, does not experience any significant resistive changes upon application of a read voltage across the memory element;
- and
- being in electrical contact with one conductive array line from the first layer and one conductive array line from the second layer, the conductive array lines forming a unique pair for each memory plug;
- wherein both the first write mode and the second write mode are preceded by the read mode to determine the resistive state of the memory element.
9 more elements
A cross point memory array comprising:
- a first group of substantially parallel conductive array lines;
- a second group of substantially parallel conductive array lines, oriented substantially perpendicular to the first group of parallel conductive lines;
- and
- a plurality of memory plugs located at the intersections of the first group of parallel conductive array lines and the second group of parallel conductive array lines;
- wherein each memory plug includes a memory element that switches from a first resistance state to a second resistance state upon application of a first write voltage pulse to the memory element in a first write mode, reversibly switches from the second resistance state back to the first resistance state upon application of a second write voltage pulse to the memory element in a second write mode, and does not experience any significant resistive changes upon application of a read voltage in a read mode.
2 more elements
A method of performing a write operation on a cross point memory array comprising:
- receiving an instruction to put a memory plug in a desired resistive state;
- applying a read voltage to a pair of conductive array lines that uniquely identifies the memory plug in the cross point array;
- determining the memory plug's resistive state;
- applying a first write voltage pulse to the pair of conductive array lines only if the memory plug is in a first resistive state and the desired resistive state is a second resistive state, the first voltage pulse being useful to switch the resistive state of the memory plug form the first resistive state to the second resistive state;
- and
- applying a second write voltage pulse to the pair of conductive array lines only if the memory plug is in a second resistive state and the desired resistive state is a first resistive state, the second voltage pulse being useful to switch the resistive state of the memory plug from the second resistive state to the first resistive state.
3 more elements
Dependencies are inferred from the claim text.