Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions

A method of increasing the efficiency of the execution of digital signal processing (DSP) instructions and reduced instruction set computer (RISC) control instructions, the method comprising:

• fetching at least one single instruction from a program memory;
• reading the at least one single instruction, the at least one single instruction being one of a DSP instruction or a RISC control instruction;
• generating DSP control signals to control the execution of the DSP instruction by at least one signal processing unit;
• controlling the flow of operands and results between the at least one signal processing unit and a data memory using a reduced instruction set computer (RISC) control unit;
• and
• generating RISC control signals to control the execution of the RISC control instruction.

A unified RISC/DSP pipeline controller to increase the efficiency of the execution of digital signal processing (DSP) instructions and reduced instruction set computer (RISC) control instructions, the unified pipeline controller comprising:

• a fetch control stage to generate addresses coupled to a program memory to read a single instruction, the program memory to store at least one single instruction being one of a DSP instruction or a RISC control instruction;
• a decoder stage to decode the DSP instruction or the RISC control instruction;
• and
• a plurality of execution stages coupled to at least one signal processing unit to provide DSP control signals to the at least one signal processing unit to control the execution of the DSP instruction by the at least one signal processing unit.