Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same

A method of designing a circuit containing a plurality of Test Access Ports (TAPs), each said TAP having a Test Data Input (TDO), a Test Data Output (TDO), a Test Mode Select (TMS) input, a clock input and a Test Reset (TRSTN) input, each said TAP having an instruction register and at least one test data register, the method comprising the steps of:

• selecting one TAP as a master TAP;
• arranging the remaining secondary TAPs into at least one group having a group TDI and a group TDO, with the TAPs in each group being serially connected in a daisy chain between said group TDI and group TDO;
• determining the instruction register length of each said group;
• providing said master TAP instruction register with a number of register elements equal to that of the longest group instruction register length plus a number of bits, defining a selection code register, for storing a selection code for use in selecting one of said groups for data transfer;
• providing, for each said group, a group padding register having an input connected to the circuit TDI, an output and having a length equal to the length of said master TAP instruction register less the instruction register length of said group;
• providing, for each said group, a TMS gating circuit responsive to a circuit TMS input and to a predetermined selection code representative of said group for producing and applying a group TMS signal to each TAP of said group, said group TMS signal being the same as the circuit TMS input when an applied selection code corresponds to the predetermined group selection code corresponding to said group and, otherwise, said TMS signal being inactive, said TMS gating circuit having a TMS input connected to said circuit TMS input;
• a selection code input connected to said master TAP selection code register and an output connected to the TMS input of all TAPs of the group;
• providing, for each said group, a TDI multiplexer circuit for selectively connecting the group TDI to either the circuit TDI when a test data register in the group are being accessed, or to the output of said group padding register when the instruction registers of the group are being accessed and connecting the output of said TDI multiplexer circuit to the group TDI of the first TAP in the daisy-chain;
• providing a TDO multiplexer circuit for selectively connecting the group TDO of the group specified by a selection code loaded in said selection code register;
• providing, for said master TAP, an update gating circuit responsive to a predetermined group selection code in said selection code register and corresponding to said master TAP for allowing the update of a master TAP update register, and, otherwise, for suppressing the update register except for selection code register bits;
• and
• adding a reset gating circuit to said master TAP for controlling the test reset input of remaining TAPs such that said remaining TAPs are reset when the master TAP is reset.

In a method of designing a circuit containing a plurality of Test Access Port (TAP) interfaces, each said TAP having a Test Data Input (TDI), a Test Data Output (TDO), a Test Mode Select (TMS) input, a Test Clock Input and a Test Reset input (TRSTN), an instruction register and at least one test data register, the method comprising the steps of:

• providing a master TAP for at least controlling data transfer operations with other TAPs in said circuit;
• connecting the master TAP test inputs and output to corresponding circuit test inputs and output;
• arranging said TAPs into at least two groups of one or more TAPs serially connected between a group TDI and a group TDO, said master TAP being the sole member of one of said groups;
• providing said master TAP with:
• an instruction register having a length equal to the sum of the length of the instruction registers of the longest group instruction register plus a predetermined number of bits forming a TAP selection code register for storing a group selection code for selecting one of the groups for data transfer;
• a TDO circuit responsive to the group selection code for selectively connecting the group TDO of one of the groups to the circuit TDO;
• and
• for each said group:
• a padding register having an output connected to the group TDI input of said each group and an input connected to the circuit TDI;
• a TMS circuit responsive to predetermined group selection code for said each group for producing a group TMS;
• and
• a TDI circuit responsive to a shift state signal for either connecting a circuit TDI to the group TDI or for connecting the output of said padding register to the group TDI.

In a circuit having a plurality of Test Access Port (TAP) interfaces, each interface having test connections including a Test Data Input (TDI), a Test Data Output (TDO), a Test Mode Select (TMS) input, a Test Clock Input and a Test Reset input (TRSTN), an instruction register and at least one test data register, comprising:

• one of said TAPs having test connections serving as a circuit test interface, said one TAP having:
• an instruction register having a length equal to the length of the longest instruction register plus a predetermined number of bits for storing a TAP selection code for selecting one of the TAPs;
• a TDO circuit responsive to said TAP selection code for selectively connecting the TDO of one of the TAPs to the circuit TDO;
• and
• said one TAP further including, for each other TAP in said circuit:
• a padding register having a length equal to the length of said instruction register of said one TAP less the length of the instruction register of said each other TAP and having an input connected to the circuit TDI, and an output;
• a TMS circuit responsive to a predetermined TAP selection code associated with said each other TAP and a TMS signal applied to a circuit TMS input for producing a TAP TMS signal for said each other TAP;
• and
• a TDI circuit responsive to a shift state signal for selectively connecting the TDI of said other TAP to the circuit TDI or to the output of said padding register.

In a circuit having a plurality of Test Access Port (TAP) interfaces, each said TAP having a TAP Test Data Input (TDI), a TAP Test Data Output (TDO), a TAP Test Mode Select (TMS) input, a TAP clock input and a TAP Test Reset (TRSTN) input, a TAP instruction register and at least one TAP test data register, said circuit having a circuit Test Data Input, a circuit Test Data Input, a circuit Test Data Output, a circuit Test Mode Select input, a circuit Test Clock input and a circuit reset input, the improvement comprising:

• one of said TAPs being a master TAP;
• said TAPs being arranged into at least two groups of one or more TAPs having a group TDI and a group TDO, the TAPs in each said group being daisy-chained between said group TDI and group TDO such that the TDI of each TAP is connected to the TDO of the preceding TAP in the chain, said master TAP being the sole member of one of said groups;
• said master TAP having an instruction register bit length equal to the bit length of the longest group instruction register chain length of said groups plus a predetermined number of bits, defining a selection code register, for storing a group selection code for selecting any one of said groups;
• a TDO multiplexer circuit responsive to said selection code for selecting the group TDO of the group corresponding to a selection code loaded into said master TAP selection code register for connection to said circuit TDO;
• said master TAP having, for each said group:
• a padding register having a length equal to the length of said master TAP instruction register less the length of the instruction register chain length of said group, an input connected to the circuit TDI, and an output;
• a TDI multiplexer circuit responsive to a shift state signal for selectively connecting said group TDI to either said circuit TDI when a test data register of said group is to be accessed or to said output of said padding register when an instruction register in said group is to be accessed;
• a TMS gating circuit responsive to a predetermined group selection code, a predetermined master TAP state signal and said circuit TMS signal for producing and applying a group TMS signal to the TMS input of each TAP in said group, said group TMS signal being the same as the circuit Test Mode Select signal when said current selection code corresponds to said predetermined group selection code or said master TAP is in a reset state, and, otherwise, said group TMS signal being inactive;
• an update signal gating circuit responsive to said selection code for suppressing the update of all bits, except for the bits defining said group selection code, of said master TAP instruction register when the current selection code is other than the predetermined selection code associated with said master TAP and for updating said master TAP instruction register when said the current selection code corresponds to the predetermined group selection code associated with said master TAP;
• a reset signal gating circuit responsive to a reset signal applied to the circuit test reset input for controlling the test reset input of said remaining TAPs for resetting said remaining TAPs when said master TAP is reset.

A method of controlling a circuit having a plurality of Test Access Port (TAP) interfaces in which one of said TAPs is connected to circuit test inputs and outputs and each said TAP interface includes a TAP Test Data Input (TDI), a TAP Test Data Output (TDO), a TAP Test Mode Select (TMS) input, a TAP clock input and a TAP reset input (TRSTN), an instruction register and at least one test data register, said TAPs being arranged into two or more groups of TAPs, each group having a group TDI and a group TDO and one or more TAPs serially connected there between, the method comprising:

• (a) loading each test instruction into the instruction register of said one of said TAPs, each instruction including a group selection code specifying the TAP to be accessed in the next instruction;
• (b) connecting the group TDO of the group having a predetermined TAP selection code corresponding to the TAP selection code stored in said instruction register to the TDO of said circuit;
• (c) connecting the group TDI of all groups to the circuit TDI when accessing a test data register of a group;
• (d) connecting the group TDI of all groups to a serial output of a respective padding register when an instruction register is to be accessed;
• and
• (e) applying a sufficient number of clock cycles to shift data into said test data register or an instruction into the instruction register of the specified TAP;
• and
• (f) repeating steps (a)-(f) for each additional data transfer operation.

A program product for use in designing a circuit having a plurality of Test Access Port (TAP) interfaces, each TAP having a Test Data Input (TDI), a Test Data Output (TDO), a Test Mode Select (TMS) input, a Test Clock Input, a Test Reset input (TRSTN), an instruction register and at least one test data register, the program product comprising:

• a computer readable storage medium;
• means recorded on the medium for reading a circuit description of said circuit having a description of each said TAP;
• means recorded on the medium for determining the instruction register bit length of the instruction register of each said TAP;
• means recorded on the medium for inserting a description of a master TAP into a description of said circuit including:
• connecting master TAP test ports to corresponding circuit test ports;
• arranging said TAPs into at least two groups and serially connecting the TAPs in each group between a group TDI and a group TDO with the master TAP being the sole member of one of said groups;
• for each group containing secondary TAPs:
• connecting the group TDI of each group to a master TAP group TDI output for the group;
• connecting the group TDO of each group to a master TAP group TDO input for the group;
• determining the instruction register chain length of the group by summing the length of the instruction register bit length of each TAP in the group;
• adding to the description of the master TAP:
• a master TAP instruction register having a length equal to instruction register chain length of the group having the longest instruction register chain plus a predetermined number of bits forming a TAP selection code register for storing a group selection code for selecting one of the groups for data transfer;
• a description of a TDO circuit receiving for input the TDO output of each group and an output connected to the circuit TDO and a select input receiving the group selection code for selectively connecting the group TDO of one of the groups to the circuit TDO;
• and
• for each group:
• a description of a padding register having an input connected to a circuit TDI and an output connected to the group TDI of the group;
• a description of a TMS circuit responsive to a predetermined group selection code for producing a group TMS;
• and
• a description of said TDI circuit responsive to a shift state signal for either connecting the circuit TDI to the group TDI or for connecting the output of said padding register to the group TDI.