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AssigneeInternational Business Machines Corporation
InventorsGordon Taylor Davis, Marco C. Heddes, Ross Boyd Leavens, Mark Anthony Rinaldi
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An embedded processor complex contains multiple protocol processor units (PPUs). Each unit includes at least one, and preferably two independently functioning core language processors (CLPs). Each CLP supports dual threads thread which interact through logical coprocessor execution or data interfaces with a plurality of special purpose coprocessors that serve each PPU. Operating instructions enable the PPU to identify long and short latency events and to control and shift priority for thread execution based on this identification. The instructions also enable the conditional execution of specific coprocessor operations upon the occurrence or non occurrence of certain specified events.
In the operation of an embedded processor complex for controlling the progammability of a network processor, the processor complex including a plurality of protocol processor units (PPUs), each PPU containing multiple core language processors (CLPs), each CLP having at least two code threads, each PPU utilizing a plurality of coprocessors useful for executing specific tasks for the PPU, multiple logical coprocessor interfaces to provide access between each CLP and the coprocessors, and two arbiters between the CLPs and the coprocessors, wherein the coprocessors are selected from the group including a tree search coprocessor, a checksum coprocessor, a stringcopy coprocessor, an enqueue coprocessor, a datastore coprocessor, a CAB coprocessor, a counter coprocessor and a policy coprocessor, and wherein one of the arbiters is a coprocessor execution interface arbiter to determine the priority between multiple code threads.
In the operation according to clam 3, wherein the FIFO buffer is between each CLP and the policy coprocessor.
A network processing system including an embedded processor complex for controlling the programmability of a network processor, said embedded processor complex including a plurality of protocol processor units (PPUs), each PPU containing:
A method of controlling the execution of instructions within an embedded processor complex which contains a plurality of protocol processor units (PPUs), each protocol processor unit containing at least two core language processors (CLPs), each CLP having at least two code threads, wherein the threads are used by each of said PPUs for executing specific tasks for the PPUs, and used by multiple logical coprocessor interfaces coupled to said plurality of coprocessors to provide access between the coprocessors and cach CLP, and two arbiters between the CLPs and the coprocssors, and including the use of dedicated coprocessors that support the multiple code threads of the PPU, and wherein one or more of the coprocessors are selected from the group including a tree search coprocessor, checksum coprocessor, stringcopy coprocessor, enqueue coprocessor, datastore coprocessor, CAB coprocessor, counter coprocessor and policy coprocessor, and wherein a coprocessor data interface arbiter serves to determine the priority between data threads.
In the operation of an embedded processor complex for controlling the programmability of a network processor, the processor complex including a plurality of protocol processor units (PPUs), each PPU containing multiple core language processors (CLPs), each CLP having at least two code threads, each PPU utilizing a plurality of coprocessors useful for executing specific tasks for the PPU, multiple logical coprocessor interfaces to provide access between each CLP and the coprocessors, and two arbiters between the CLPs and the coprocessors, wherein the coprocessors are selected from the group including a tree search coprocessor, a checksum coprocessor, a stringcopy coprocessor, an enqueue coprocessor, a datastore coprocessor, a CAB coprocessor, a counter coprocessor and a policy coprocessor, and wherein one of the arbiters is a coprocessor data interface arbiter that determines the priority between data threads.
A network processing system including an embedded processor embedded processor complex for controlling the programmability of a network processor, said complex including a plurality of protocol processor units (PPUs), each of said PPUs containing:
A method of controlling the execution of instructions within an embedded processor complex which contains a plurality of protocol processor units (PPUs), each protocol processor unit containing at least two core language processors (CLPs), each CLP having at least two code threads, wherein the threads are used by each of said PPUs for executing specific tasks for the PPUs, and used by multiple logical coprocessor interfaces coupled to said plurality of coprocessors to provide access between the coprocessors and each CLP, and two arbiters between the CLPs and the coprocessors, and the step of providing instructions that enable the system to identify long latency events and short latency events according to the expected response time to a particular coprocessor command, and to grant full control to another thread when execution of an active thread stalls due to a long latency event, or to grant temporary control to another thread when execution of an active thread stalls due to a short latency event.
Dependencies are inferred from the claim text.