Floating point unit for multiple data architectures

A floating point unit for supporting a first floating point architecture and a second floating point architecture, the first and second floating point architectures each having at least one format, the unit comprising:

• an internal floating point format compatible with both the first and second floating point architectures, and sharing the fraction bits and sign bit with both of the floating point architectures;
• a first converter to convert an operand of the first floating point architecture type to the internal floating point format by multiplexing the exponent bits of the operand, and to convert an operand of the second floating point architecture type to the internal floating point format by multiplexing the exponent bits of the operand, wherein said first converter operates without incurring additional clock cycles when said first floating point architecture type is binary, said first converter operates without incurring additional clock cycles when said first floating point architecture type is hexadecimal, said first convener operates without incurring additional clock cycles when said second floating point architecture type is binary, and said first convertor operates without, incurring additional clock cycles when said second floating point architecture type is hexadecimal;
• a floating point unit having an internal data-flow for the internal floating point format that supports the converted data of both the first and second floating point architectures, and that performs floating point operations on data formatted in the internal floating point format by the first converter;
• and
• a second converter to convert data of the internal floating point format into data of the first floating point architecture by multiplexing the exponent bits of the operand, and to convert data of the internal floating point format into data of the second floating paint architecture by multiplexing the exponent bits of the operand.

A method for processing data corresponding to a plurality of floating point architectures, comprising:

• determining a type of a floating point architecture;
• converting the exponent of the data corresponding to the determined architecture into an internal floating point format by:
• correcting the radix point location of the exponent data, and pre-aligning the corrected exponent data, wherein said converting is performed by a multiplexor for multiplexing the exponent data without incuring additional clock cycles when said determined architecture is binary and said converting is performed by the multiplexor without incurring additional clock cycles when said determined
• performing arithmetic computations on the converted data;
• re-converting the exponent of the computation data by;
• re-correcting the radix point location of the exponent of the computed data, and
• post-aligning the re-corrected exponent of the computed data;
• and outputting the re-converted data to thereby provide floating point data corresponding to the original floating point architecture without incurring a delay beyond that required to compute the resulting output in the internal floating point format.