US 6,829,160 B1 · Magnetic ram cell with amplification circuitry and MRAM memory array formed using the MRAM cells

Abstract

A magnetic random access memory (MRAM) cell and a memory array formed from the MRAM cells are disclosed. The MRAM cell includes a magnetic tunneling junction and a transistor. The magnetic tunneling junction includes a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer. The gate of the transistor is coupled to a first end of the magnetic tunneling junction. The source of the transistor is coupled to a second end the magnetic tunneling junction. The drain of the transistor is coupled with an output for reading the magnetic memory cell. During reading, a read current is applied to the magnetic tunneling junction and the transistor is preferably operated in a saturation region.

Claims9

Dependent claims

A magnetic memory cell comprising:

a magnetic tunneling junction including a first ferromagnetic layer, a second ferromagnetic layer and an insulating layer between the first ferromagnetic layer and the second ferromagnetic layer;
and
a transistor having a source, a drain and a gate, the gate of the transistor being coupled to a first end of the magnetic tunneling junction, the source of the transistor being coupled to a second end the magnetic tunneling junction, the drain of the transistor being coupled with an output for reading the magnetic memory cell.

A magnetic memory comprising:

a plurality of memory cells arranged in an array including a plurality of rows and a plurality of columns, each of the plurality of memory cells including a magnetic tunneling junction and a transistor having a source, a drain and a gate, the gate of the transistor being coupled to a first end of the magnetic tunneling junction, the source of the transistor being coupled to a second end of the magnetic tunneling junction, the drain of the transistor being coupled with an output for reading the magnetic memory cell;
a plurality of row lines coupled to the plurality of rows, the plurality of row lines coupled to gate of the transistor in each of the plurality of memory cells in the plurality of rows;
a row selector coupled to the plurality of row lines for selecting between the plurality of row lines and providing a current to a selected row of the plurality of rows.

Dependencies are inferred from the claim text.

Magnetic ram cell with amplification circuitry and MRAM memory array formed using the MRAM cells

Life of this patent

Magnetic ram cell with amplification circuitry and MRAM memory array formed using the MRAM cells

Life of this patent

Abstract

Claims9