Class AB operational amplifier with split folded-cascode structure and method

A method of accurately controlling quiescent bias current in a class AB output stage of an amplifier, comprising:

• (a) providing the first class AB output stage with a pull-up transistor having a gate coupled to a first gate drive conductor and a drain coupled to a first output conductor and also providing a pull-down transistor having a gate coupled to a second gate drive conductor and a drain coupled to the first output conductor;
• (b) providing a split input transistor circuit structure for a first side of a differential input stage by providing first and second input transistors each having a gate coupled to a first input of the amplifier, and also providing a third input transistor having a gate coupled to a second input of the amplifier;
• (c) providing a split folded cascode circuit structure having a common gate configuration by providing first and second gate-coupled cascode transistors having drains coupled to the first and second gate drive conductors, respectively, and coupling sources of the first and second gate-coupled cascode transistors to drains of the first and second input transistors, respectively;
• (d) providing a third cascode transistor having a gate connected to the reference signal conductor and coupling a source of the third cascode transistor to a drain of the third input transistor by means of a third conductor;
• and
• (e) sensing current in the pull-up and pull-down transistors, comparing the sensed current with a predetermined reference current to produce an error signal representing a difference between the sensed current and the predetermined reference current, amplifying the error signal to produce an error current signal, and introducing the error current signal into a source of one of the first and second gate-coupled cascode transistors.

A method of accurately controlling quiescent bias current in a pull-up transistor and a pull-down transistor of a class AB output stage of an amplifier, comprising:

• (a) providing a first class AB output stage including the pull-up transistor with a gate coupled to a first gate drive conductor and a drain coupled to a first output conductor and the pull-down transistor with a gate coupled to a second gate drive conductor and a drain coupled to the first output conductor, and
• (b) providing substantially equal amounts of differential amplification to both an output of a differential input stage of the amplifier and an output of a class AB control circuit of the amplifier by
• i. providing a split input transistor circuit structure for a first side of the differential input stage by providing first and second input transistors each having a gate coupled to a first input of the amplifier, and also providing a third input transistor having a gate coupled to a second input of the amplifier,
• ii. providing a split folded cascode circuit structure having a common gate configuration by providing first and second cascode transistors each having a gate coupled to a reference signal conductor, the first and second cascode transistors having drains coupled to the first and second gate drive conductors, respectively,
• iii. providing a third cascode transistor having a gate connected to the reference signal conductor and a source coupled to a drain of the third input transistor,
• iv. coupling drains of the first, second, and third input transistors to the sources of the first, second and third cascode transistors, and
• v. sensing current in the pull-up and pull-down transistors, comparing the sensed current with a predetermined reference current to produce a differential error signal representing a difference between the sensed current and the predetermined reference current, amplifying the differential error signal to produce a differential error current signal, and introducing the differential error current signal into the sources of the first and second cascode transistors.

Circuitry for accurately controlling quiescent bias current in a class AB output stage of an amplifier, comprising:

• (a) a pull-up transistor in the first class AB output stage having a gate coupled to a first gate drive conductor and a drain coupled to a first output conductor and a pull-down transistor in the first class AB output stage having a gate coupled to a second gate drive conductor and a drain coupled to the first output conductor;
• (b) means for providing a split input transistor circuit structure for a first side of a differential input stage including first and second input transistors each having a gate coupled to a first input of the amplifier, and also including a third input transistor having a gate coupled to a second input of the amplifier, sources of the first, second, and third input transistors being coupled to a current source;
• (c) means for providing a split folded cascode circuit structure having a common gate configuration including first and second gate-coupled cascode transistors having drains coupled to the first and second gate drive conductors, respectively, sources of the first and second gate-coupled cascode transistors being coupled to drains of the first and second input transistors, respectively;
• (d) a third cascode transistor having a gate connected to the reference signal conductor, a source of the third cascode transistor being coupled to a drain of the third input transistor by means of a third conductor;
• and
• (e) means for sensing current in the pull-up and pull-down transistors, means for comparing the sensed current with a predetermined reference current to produce an error signal representing a difference between the sensed current and the predetermined reference current, means for amplifying the error signal to produce an error current signal, and means for introducing the error current signal into a source of one of the first and second gate-coupled cascode transistors.