Back to results
US 6,826,717 B1Granted
Synchronization of hardware and software debuggers
AssigneeAltera Corporation
InventorsAndrew Draper, Edward Flaherty
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeAltera Corporation
InventorsAndrew Draper, Edward Flaherty
Estimating the term…
A technique synchronizes logic signals captured in a PLD portion of a PLD system having both a microprocessor and PLD circuitry with executed instructions captured from a microprocessor portion. One or more signal lines connects the microcontroller portion with the PLD portion for transmitting signals between the two portions corresponding to debug operations in each portion. Conventional electronic circuits employing microprocessors and PLD's use independent debugging techniques, either of which are incapable of reflecting the complete state of the circuit at a selected time. Combined processor and PLD systems employ independent clocks for each portion, thus creating additional problems in synchronizing logic state traces in the PLD with the microprocessor instruction traces. The present invention provides a direct signals from the PLD portion to the microcontroller portion upon the occurrence of events relating to debugging and debug modes of the microprocessor. In one embodiment, the PLD portion is configured to send the output from a counter to a trace module in the microcontroller portion. The periodic and variably valued output signal from the PLD portion enables software in an external host computer connected to the combined circuit to match a debug trace from the microprocessor to selected events occurring within the PLD portion. In another embodiment, a signal is transmitted from the microcontroller portion to the PLD portion and an embedded logic analyzer is configured to respond to the signal by performing a post-trigger scan. This scan captures the states of selected logic in the PLD portion and may provide the data to a user through software operating on a host computer connected to the PLD portion, often through a JTAG port.
A programmable logic device (“PLD”) system comprising:
A programmable logic device (“PLD”) system comprising:
A method for debugging a programmable logic device (PLD) system comprising a microcontroller portion and a PLD portion, said method comprising:
A method for debugging a programmable logic device (PLD) system containing a microprocessor and a PLD portion, said method comprising:
Dependencies are inferred from the claim text.