Low power logic gate

An address decoder comprising:

• a charge holding device;
• a charging circuit for selectively providing a predetermined charge for the charge
• holding device, the charging circuit comprising an electrically switched connection of a predetermined voltage potential to the charge holding device through a series diode;
• an address decoder output that is a function of charge on the charge holding device;
• and
• a plurality of address lines, the plurality of address lines being electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of address lines is a first voltage potential.

A memory array comprising:

• an array of memory cells;
• a plurality of address lines for addressing the memory cells;
• an address decoder for selection of the address lines, the address decoder comprising;
• a charge holding device;
• a charging circuit for selectively providing a predetermined charge for the charge holding device, the charging circuit comprising an electrically switched connection of a predetermined voltage potential to the charge holding device through a series charging diode;
• an address decoder output that is a function of charge on the charge holding device;
• and
• a plurality of address lines, the plurality of address lines being electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of address lines is a first voltage potential.

A computing device comprising:

• a central processing unit;
• a memory array that can be accessed by the central processing unit;
• an array of memory cells;
• a plurality of address lines for addressing the memory cells;
• an address decoder for selection of the address lines, the address decoder comprising;
• a charge holding device;
• a charging circuit for selectively providing a predetermined charge for the charge holding device, the charging circuit comprising an electrically switched connection of a predetermined voltage potential to the charge holding device through a series diode;
• an address decoder output that is a function of charge on the charge holding device;
• and
• the plurality of address lines being electrically connected to the charge holding device so that the charge of the charge holding device is modified if any of the plurality of address lines is a first voltage potential.