Stress inducing spacers
AssigneeInternational Business Machines Corporation
InventorsDureseti Chidambarrao, Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman, Xavier Baie
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AssigneeInternational Business Machines Corporation
InventorsDureseti Chidambarrao, Omer H. Dokumaci, Bruce B. Doris, Jack A. Mandelman, Xavier Baie
Estimating the term…
A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both the gate and the substrate and impose forces on adjacent substrate areas. Another embodiment comprises compressive stresses imposed in the plane of the channel using SOI sidewall spacers made of polysilicon that is expanded by oxidation. The substrate areas under compression or tension exhibit charge mobility characteristics different from those of a non-stressed substrate. By controllably varying these stresses within NFET and PFET devices formed on a substrate, improvements in IC performance have been demonstrated.
A spacer structure for devices formed in a substrate, the devices including devices of a first conductivity type and devices of a second conductivity type, the devices each having a channel for conducting charge in a longitudinal direction and each having a gate terminal adjacent the channel, the structure comprising:
Dependencies are inferred from the claim text.