Semiconductor storage device and test system
AssigneesHitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
InventorMasaya Muranaka
Life of this patent
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Abstract
A memory circuit having a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit for performing an operation of selecting an address is provided with a computing circuit for generating an address signal for test; a packet decoder for designating the kind of computation to the computing circuit; and an input circuit for supplying a test signal comprising a plurality of bits for designating a test operation to the packet decoder.
Claims14
A semiconductor memory device comprising:
- a memory circuit having a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit line pairs and a peripheral circuit which performs an operation of selecting an address;
- an arithmetic circuit which generates an address signal to test said memory circuit;
- a first packet decoder which designates the kind of operation to said arithmetic circuit;
- and
- an input and output circuit which supplies a test signal comprising a plurality of bits which designate a testing operation to said first packet decoder.
A test system for a wafer on which a plurality of memory chips are mounted, comprising:
- an intermediate board having a plurality of POGO pins with which one ends of pads related to said test of a plurality of memory chips formed on said wafer come into contact;
- a testing board having an electrode coming into electrical contact with the other ends of the plurality of POGO pins provided for said intermediate board, on which a semiconductor integrated circuit device for control to generate various signals for a test on the plurality of memory chips is mounted;
- and
- a central control unit which supplies a test control signal to the semiconductor integrated circuit device for control provided on said testing board,
- wherein each of the memory chips comprises a memory circuit, an arithmetic circuit which generates an address signal to test said memory circuit, a packet decoder which designates the kind of operation to said arithmetic circuit, and an input circuit which supplies a test signal comprising a plurality of bits to designate a testing operation to said packet decoder, and
- wherein said memory circuit includes a memory cell array in which a plurality of memory cells are provided at intersection points of a plurality of word lines and a plurality of bit lines pairs, and a peripheral circuit to perform an operation selecting an address.
Dependencies are inferred from the claim text.