US 6,823,001 B1 · Dual stage communication processor

Abstract

A communications processor is presented that is capable of receiving a potentially degraded data transmission signals operating at high transmission rates and generating an improved data transmission signal in a manner that allows the signals to be transmitted over longer distances than is otherwise possible using conventional methods. The communications processor includes a decoding mechanism configured to compensate for amplitude and phase distortions of the data transmission signal, to split the corrected data signal into component data signals, to generate a data clock reference signal based on the data transmission signal and the external clock reference signal, and to convert the component data signals into digital component data signals synchronized to the data clock reference signal. The communications processor further includes an encoding mechanism configured to receive the digital component data signals and the data clock reference signal and to convert the digital component data signals into analog component data signals. The communications processor then selectively outputs at least one of the analog component data signals as the improved data transmission signal.

An apparatus for receiving a data transmission signal operating at a predetermined transmission rate and generating an improved data transmission signal, said apparatus comprising:

a decoding mechanism configured to receive said data transmission signal and a clock reference signal having a predetermined clock rate matching said predetermined transmission rate of said data transmission signal, said decoding mechanism being configured to compensate for amplitude and phase distortions of said data transmission signal and produce a corrected data signal, to split said corrected data signal into component data signals, to generate a data clock reference signal based on said data transmission signal and said clock reference signal, and to convert said component data signals into digital component data signals synchronized to said data clock reference signal;
a first coupler and impedance matching mechanism configured to couple said data transmission signal to said decoding mechanism, said first coupler and impedance matching mechanism including a transformer having primary and secondary windings isolated from a ground connection, a resistive element matching the impedance of a transmission facility conveying said data transmission signal, and a high frequency coupling mechanism for filtering said coupled data transmission signal;
an encoding mechanism coupled to said decoding mechanism, said encoding mechanism configured to receive said digital component data signals and said data clock reference signal and to convert said digital component data signals into analog component data signals,
wherein said decoding mechanism comprises:
an attenuating mechanism coupled to said first coupler and impedance matching mechanism, said attenuating mechanism configured to initially adjust the amplitude of said coupled data transmission signal to a predetermined level,
a gain and equalizing mechanism coupled to said attenuating mechanism, said gain and equalizing mechanism configured to adjust the gain and compensate for amplitude and phase distortions of said coupled data transmission signal,
a signal splitting mechanism to split the corrected data transmission signal into component data signals,
a slicing mechanism coupled to said gain and equalizing mechanism and said signal splitting mechanism, said slicing mechanism configured to convert said component data signals into digital component data signals,
a combiner mechanism coupled to said slicing mechanism, said combiner mechanism configured to combine said digital component data signals into a composite digital data signal, and a
phase lock loop mechanism configured to receive said composite digital data signal, lock into a frequency and phase of said composite digital data signal, and generate said data clock reference signal, said phase lock loop mechanism including a phase detector to detect the phase of said composite digital data signal, a loop filter to filter out high frequency noise components of said composite digital signal, and a voltage controlled oscillator for generating said frequency and phase information from said composite digital signal, and
wherein said apparatus outputs at least one of said analog component data signals as the improved data transmission signal.

8 more elements

Dual stage communication processor

Life of this patent

Dual stage communication processor

Life of this patent

Abstract

Claims20