Semiconductor device and method of manufacturing the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTadaharu Minato, Tetsuya Nitta
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AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTadaharu Minato, Tetsuya Nitta
Estimating the term…
A semiconductor device of the present invention has a pn-repeating structure that a structure in which a p-type impurity region (4) and an n-type drift region (3) are aligned side by side is repeated twice or more, and a low concentration region which is either p-type impurity region (4) or n-type drift region (3) located at the outermost portion of this pn-repeating structure has the lowest impurity concentration or has the least generally effective charge amount among all the p-type impurity regions (4) and n-type drift regions (3) forming the pn-repeating structure. Thereby, the main withstand voltage of a power semiconductor device to which a three dimensional multi-RESURF principle is applied, wherein the element withstand voltage is specifically in the broad range of 20 to 6000 V, can be improved and the trade-off relationship between the main withstand voltage and the ON resistance can also be improved, so that an inexpensive semiconductor device of which the power loss is small and of which the size of the chip is small can be obtained. In addition, a trench of a dotted line trench (DLT) structure and a manufacturing method corresponding to this can be used, so that a semiconductor device with a good yield can be obtained at low cost.
A semiconductor device having a repeating structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice, or more, in a semiconductor substrate of the first conductive type, wherein
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A manufacturing method for a semiconductor device having a structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice or more in a semiconductor substrate of the first conductive type, characterized in that
A semiconductor device having a repeating structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice, or more, in a semiconductor substrate of the first conductive type, wherein
A semiconductor device having a repeating structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice, or more, in a semiconductor substrate of the first conductive type, wherein
A semiconductor device having a repeating structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice, or more, in a semiconductor substrate of the first conductive type, wherein
A semiconductor device having a repeating structure wherein a structure where a first impurity region of a first conductive type and a second impurity region of a second conductive type are aligned side by side is repeated twice, or more, in a semiconductor substrate of the first conductive type, wherein
Dependencies are inferred from the claim text.