Buffering data transfer between a chipset and memory modules

A method, comprising:

• isolating a memory interface between a chipset and memory modules, where said isolating divides the memory interface into first and second sub-interfaces;
• and
• configuring said first and second sub-interfaces to properly transfer data between the chipset and the memory modules, such that the first and second sub-interfaces operate independently but in synchronization with each other,
• wherein said first and second sub-interfaces are configured in such a manner that the first sub-interface is operated at different voltage level and at higher frequency than the second sub-interface.

A system, comprising:

• a memory interface between a chipset and at least one memory module;
• and
• at least one buffer disposed in said memory interface to divide said memory interface into first and second sub-interfaces,
• where said first and second sub-interfaces are configured in such a manner that the first sub-interface is operated at different voltage level and at higher frequency than the second sub-interface.