Apparatus and method for a sense amplifier circuit that samples and holds a reference voltage
AssigneeAdvanced Micro Devices, Inc.
InventorMichael Achter
Life of this patent
Estimating the term…
Abstract
A sense amplifier circuit. Specifically, a sample and hold sense amplifier circuit that is capable of sampling and holding a reference voltage comprises a reference voltage sampler circuit coupled to a cross-coupled inverter latch. The reference voltage sampler circuit is coupled to a bitline associated with a memory cell. The reference voltage is sampled from a precharge voltage taken off the bitline, and is used to read a state on a memory cell. The cross-coupled inverter latch is also coupled to the bitline, and is used for amplifying a voltage difference between an output voltage from the cross-coupled inverter latch and the reference voltage. The output voltage is based on a static bitline voltage from the bitline.
Claims26
A sample and hold sense amplifier circuit comprising:
- a reference voltage sampler circuit coupled to a bitline of a memory cell, said reference voltage sampler circuit for sampling a reference voltage from a precharge voltage of said bitline, said reference voltage for reading a state on a memory cell;
- a cross-coupled inverter latch coupled to said reference voltage sampler circuit and coupled to said bitline, said cross-coupled inverter latch for amplifying a voltage difference between an output voltage of said cross-coupled inverter latch and said reference voltage, said output voltage being based on a static bitline voltage from said bitline.
A sample and hold sense amplifier circuit comprising:
- a first pass gate transistor coupled to a bitline of a memory cell for passing voltage from said bitline, said first pass gate transistor controlled by a first precharge signal;
- a second pass gate transistor coupled to said bitline for passing said voltage from said bitline, said second pass gate transistor controlled by a second precharge signal;
- a reference voltage sampler circuit coupled to said first pass gate transistor, said reference voltage sampler for sampling and holding a reference voltage determined from a precharge voltage of said bitline;
- and
- a cross-coupled inverter latch coupled to said first pass gate transistor and said second pass gate transistor, said cross-coupled inverter latch for amplifying a voltage difference between an output voltage of said cross-coupled inverter latch and said reference voltage, said output voltage based on a static bitline voltage from said bitline.
A method for sampling and holding a reference voltage in a sensing circuit comprising:
- a) sampling said reference voltage based on a precharge voltage of a bitline during a precharge cycle, said reference voltage equal to a precharge voltage of said bitline;
- b) disabling a cross-coupled inverter latch during said precharge cycle, said cross-coupled inverter latch coupled to said bitline;
- c) holding said reference voltage after said precharge cycle;
- d) amplifying a voltage difference between an output voltage of said cross-coupled inverter latch and said reference voltage by enabling said cross-coupled inverter latch after said precharge cycle, said output voltage being based on a static bitline voltage from said bitline.
Dependencies are inferred from the claim text.