Built-in self-testing for double data rate input/output
AssigneeSun Microsystems, Inc.
InventorAmit Dinesh Sanghani
Life of this patent
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Abstract
Macro cells for a Double Data Rate (DDR) I/O interface are provided. The macro cells feature built-in self-test (BIST) functionality for testing the I/O interface at speed, without using external test or evaluation equipment. Each input or output macro cell is configured to generate test signals that are submitted to and processed by the I/O interface. The test signals are then dynamically compared to the signals produced by the interface in response to the test signals and a result is generated. The result may comprise an error signal if the test and response signals do not correspond. An I/O BIST controller may be employed to control the initiation and operation of the macro cells' self-testing.
Claims25
A self-testable double data rate (DDR) circuit, comprising:
- a stimulus generator configured to generate a test DDR signal for testing an input/output interface of a DDR circuit;
- an evaluator configured to compare said test DDR signal with a response signal produced by the input/output interface of the DDR circuit in response to said test DDR signal;
- and
- a result generator configured to generate an error condition if said response signal does not have a predetermined relationship to said test DDR signal.
A double data rate (DDR) macro cell for a self-testable input/output interface, the macro cell comprising:
- a signal generator configured to generate an input signal pattern for testing the input/output interface;
- an evaluator configured to compare said input signal pattern with an output pattern produced by the input/output interface in response to said input signal pattern;
- and
- a result generator configured to indicate an error if said output signal pattern differs from said input signal pattern;
- wherein said signal generator, said evaluator and said result generator are located on a single semiconductor chip;
- and
- wherein the input/output interface is an external interface configured to couple the single semiconductor chip to an external circuit.
A double data rate (DDR) input/output interface of a first circuit, configured to couple the first circuit to an external circuit, the DDR input/output interface comprising:
- a self-testable output macro cell;
- a self-testable input macro cell;
- and
- a self-testable clock macro cell;
- wherein self-testing of said output macro cell, said input macro cell and said clock macro cell is performed entirely within the first circuit.
A double data rate (DDR) circuit for self-testing an external input/output interface of the circuit, the circuit comprising:
- an input/output interface configured for coupling to an external circuit;
- a set of DDR output macro cells;
- a set of DDR input macro cells;
- a set of clock macro cells;
- a clock;
- and
- a controller for controlling self-testing of the external input/output interface of the DDR circuit, using the DDR output macro cells, DDR input macro cells and clock macro cells, and without communicating with any external circuit.
Dependencies are inferred from the claim text.