System-on-a-chip
AssigneeCirrus Logic, Inc.
InventorJeff Klaas
Life of this patent
Estimating the term…
Abstract
A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high speed bus 102 through a bus bridge 113. A first set of processing resources operate from high speed bus 102 and includes an external memory interface 108, a direct memory access engine 105 for controlling the exchange of information through memory interface 108, and a boot memory 104 for storing boot code. A second set of processing resources operate from peripheral bus 103 and includes an interrupt controller 115 for issuing interrupt requests to microprocessor 101, a set of programmable timers 117 for generating timed interrupt signals, and a phase locked loop 131 for generating timing signals.
Claims31
A system fabricated on a single integrated circuit chip comprising:
- a microprocessor operating from a high speed bus and providing overall control of said system;
- a peripheral bus operating in conjunction with said high speed bus through a bus bridge;
- and
- a first set of processing resources operating from said high speed bus and a second set of processing resources operating from said peripheral bus, said first set of processing resources comprising:
- a memory interface for interfacing said system with an external memory;
- a direct memory access engine for controlling the exchange of information between selected ones of said resources and said external memory through said memory interface;
- and
- a boot memory for storing boot code for initiating operation of said system;
- and said second set of processing resources comprising:
- an interrupt controller for issuing interrupt requests to said microprocessor in response to interrupt signals from selected ones of said resources;
- a set of programmable timers for generating timed interrupt signals;
- and
- a phase-locked loop for generating timing signals for timing selected operations of said system.
A system-on-a-chip based on a reduced instruction set processor core operating in conjunction with a microprocessor bus and a peripheral bus operating from the microprocessor bus through a bridge comprising:
- a first set of processing resources operating from the microprocessor bus, at least one of the first set of processing resources communicating with the microprocessor bus through a tri-state buffer interface, comprising:
- a memory controller for communicating with an external memory;
- a direct memory access engine for controlling the communications between requesting subsystems forming a part of said system and said external memory;
- circuitry for driving an external display;
- and
- first port for communicating with an external digital device;
- and
- a second set of processing resources operating from the peripheral bus, at least one of the second set of processing resources communicating with the peripheral bus through a tri-state buffer interface, comprising:
- an interrupt controller for generating interrupt requests to the microprocessor in response to interrupt signals from selected system resources;
- an interface for communicating with an external manual input device;
- second port for communicating with an external digital device;
- and
- a set of timers for selectively generating interrupt signals.
An integrated circuit comprising:
- a reduced instruction set computing microprocessor operating from an Advanced Microprocessor Bus Architecture high-speed bus;
- direct memory access circuitry operating from said high-speed bus for managing the transfer of data between selected circuits disposed on said integrated chip and memory;
- boot memory operating from said high-speed bus for booting said integrated circuit;
- an Ethernet port operating from said high-speed bus for interfacing with an external network;
- an Advanced Peripheral Bus operating from said high speed bus through a bus bridge;
- a Universal Asynchronous Receive-Transmit interface operating from said peripheral bus for interfacing with an external digital device;
- a touchscreen interface operating from said peripheral bus for interfacing with an external touchscreen device;
- and
- a watchdog timer operating from said peripheral bus for monitoring operation of said integrated circuit a graphic engine operating from said high speed bus.
Dependencies are inferred from the claim text.