Control unit having a main microprocessor and having a processor interface to a bus transceiver unit
AssigneeBayerische Motoren Werke Aktiengesellschaft
InventorsJoachim Froeschl, Josef Krammer, Anton Schedl
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Abstract
A control unit has a main microprocessor and processor interface to a bus transceiving unit, which has at least one transmit memory, one receive memory and one bus controller. Devices are provided by which the data content of the transmit memory and/or of the receive memory is reset to a defined status after each output and/or reading-in of the data stored in either memory, and before the main microprocessor outputs and/or reads in new data.
Claims16
A control unit comprising:
- a main microprocessor;
- and
- a bus transceiver unit having a processor interface, a bus controller, at least one transmit memory which transmits data content to a data bus via the bus controller, and one receive memory which receives data content from the bus via the bus controller;
- and
- means, operative after each transfer of data content from the transmit memory to the data bus or from the receive memory to the main microprocessor, for resetting the data content of at least one of the transmit memory and the receive memory to a defined status, before the main microprocessor outputs or reads in new data content.
A method for operating a control unit having a main microprocessor and a bus transceiver unit with a transmit memory which transmits data content to a data bus, a receive memory which receives data content from the data bus and a bus controller, comprising:
- after each occurrence of an output or read-in of the data content stored in the transmit memory or the receive memory, resetting the data content of the transmit or receive memory, to a defined status;
- and
- the main microprocessor outputting or reading in new data content after said resetting.
A control unit comprising:
- a microprocessor;
- and
- a bus transceiver unit comprising
- a transmit memory which receives data content from the microprocessor and transmits the contents to a bus, wherein the data content of the transmit memory is reset to a defined status after transmitting the data content to the bus;
- a receive memory which receives data content from the bus and transmits the data content to the microprocessor, wherein the data content of the receive memory is reset to a defined status after transmitting the data content to the microprocessor.
Dependencies are inferred from the claim text.