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US 6,812,734 B1Granted
Programmable termination with DC voltage level control
AssigneeAltera Corporation
InventorsSergey Shumarayev, Thomas White
Life of this patent
Estimating the term…
Abstract
Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip termination and DC level control that enable an integrate circuit to meet a variety of different high speed single-ended and differential I/O standards.
Claims17
An integrated circuit comprising:
- core logic configured to process data;
- and
- a differential interface circuit coupled between the core logic and first and second external terminals that carry data, wherein the differential interface circuit comprises:
- a differential buffer coupled to the first and second external terminals, and
- a termination network coupled between the first and second external terminals, the termination network including a first resistive branch having first and second transistors coupled in series between the first external terminal and the second external terminal, the first and second transistors having control terminals that couple to programmable control signals,
- wherein the first resistive branch further comprises a bias transistor coupled to a common node between the first and second resistors, the bias transistor being configured to bias the common node when the respective first and second transistors are off.
3 more elements
An integrated circuit comprising:
- core logic configured to process data;
- and
- a differential interface circuit coupled between the core logic and first and second external terminals that carry data, wherein the differential interface circuit comprises:
- a differential buffer coupled to the first and second external terminals, and
- a termination network coupled between the first and second external terminals, the termination network including a first resistive branch having first and second transistors coupled in series between the first external terminal and the second external terminal, the first and second transistors having control terminals that couple to programmable control signals,
- wherein the first resistive branch further comprises resistors coupled in series with the first and second transistors.
3 more elements
An integrated circuit comprising:
- core logic configured to process data;
- and
- a differential interface circuit coupled between the core logic and first and second external terminals that carry data, wherein the differential interface circuit comprises;
- a differential buffer coupled to the first and second external terminals, and
- a termination network coupled between the fist and second external terminals, the termination network including a plurality resistive branches each having first and second transistors coupled in series between the first external terminal and the second external terminal, each of the first and second transistors having control terminals that couple to programmable control signals.
- wherein the plurality of resistive branches includes a first plurality of resistive branches with transistors of a first conductivity type and a second corresponding plurality of resistive branches transistors of a second conductivity type.
3 more elements
An integrated circuit comprising:
- core logic configured to process data;
- a single ended interface circuit coupled between the core logic and a first external terminal, wherein the interface circuit includes a first buffer comprising a first pull-up path and a first pull-down path both coupled to the first external terminal;
- and
- a differential interface circuit coupled between the core logic, the first external terminal and a second external terminal, wherein the differential interface circuit comprises:
- a differential buffer coupled to the first and second external terminals, and
- a termination network coupled between the first and second external terminals having first and second transistors coupled in series between the first external terminal and the second external terminal.
3 more elements
An integrated circuit comprising:
- core logic configured to process data;
- a single ended termination circuit coupled between the core logic and a first external terminal capable of programming a first pull-up path and a first pull-down path to process data, to implement termination impedance and to perform DC level shifting at the first external terminal;
- and
- a differential termination circuit coupled between the core logic, the first external terminal, and a second external terminal, wherein the differential termination circuit comprises:
- a differential buffer coupled to the first and second external terminals, and
- a termination network coupled between the first and second external terminals having first and second transistors coupled in series between the first external terminal and the second external terminal.
3 more elements
An integrated circuit comprising:
- core logic configured to process data;
- and
- a differential interface circuit coupled between the core logic and first and second external terminals that carry data, wherein the differential interface circuit comprises:
- a differential buffer coupled to the first and second external terminals, and
- a termination network coupled between the first and second external terminals, the termination network including first, second, and third resistive branches each having two transistors coupled in series between the first external terminal and the second external terminal.
2 more elements
Dependencies are inferred from the claim text.