Memory mapping system and method

A simulation system operating in a host computer system for simulating a behavior of a circuit, the host computer system including a central processing unit (CPU), main memory, a local conductive connector coupling the CPU to main memory and allowing communication between the CPU and main memory, and a system conductive connector, the circuit having a structure and a function specified in a hardware language, the hardware language capable of describing the circuit as component types and connections, comprising:

• a software model of the circuit coupled to the local conductive connector;
• software control logic coupled to the software model and a hardware logic element, for controlling the operation of the software model and said software control logic including
• interface logic which is capable of receiving input data and a clock signal from an external process, and
• clock detection logic for detecting an active edge of the clock signal and generating a trigger signal;
• and
• said hard logic element coupled to the system conductive connector and including
• a system conductive connector controller,
• a hardware model conductive connector coupled to the system conductive connector controller,
• at least one logic device and at least one memory device coupled to the hardware model conductive connector,
• a hardware model of at least a portion of the circuit residing in at least one logic device, the hardware logic element including clock enable logic for evaluating data in the hardware model in response to the trigger signal, and
• a memory mapping system for mapping at least one memory block associated with the circuit in the hardware model from at least one logic device to at least one memory device.

A memory mapping system for mapping at least one memory block from at least one logic device to at least one memory device in a reconfigurable hardware unit, the reconfigurable hardware unit including an interconnect controller, at least one logic device for modeling at least a portion of the user design in hardware where the hardware model has at least one memory block and associated user memory interface, at least one memory device, an interconnect subsystem coupling at least one logic device, at least one memory device, and the interconnect controller, the memory mapping system comprising:

• an interconnect driver coupled to the interconnect subsystem;
• a memory block interface coupled to the interconnect driver, the interconnect subsystem, and the user memory interface to handle write/read memory access between at least one logic device and at least one memory device, wherein said at least one memory device storing the memory blocks associated with the hardware model;
• and
• an evaluation logic in each logic device coupled to the hardware model, the interconnect driver, the memory block interface, and the interconnect controller for providing evaluation control signals, the evaluation control signals used to evaluate data in the hardware model and to control write/read memory access between at least one logic device and at least one memory device via the interconnect driver and the memory block interface.