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US 6,809,598 B1Granted
Hybrid of predictive and closed-loop phase-domain digital PLL architecture
AssigneeTexas Instruments Incorporated
InventorsRobert B. Staszewski, Dirk Leipold, Kenneth Maggio
Life of this patent
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Abstract
A phase-domain digital PLL loop is implemented using a hybrid of predictive and closed-loop architecture that allows direct DCO oscillator transmit modulation in the GFSK modulation scheme of “BLUETOOTH” or GSM, as well as the chip phase modulation of the 802.11b or Wideband-CDMA. The current gain of the DCO oscillator is predicted by observing past phase error responses to previous DCO corrections. DCO control is then augmented with the “open-loop” instantaneous frequency jump estimate of the new frequency control word.
Claims25
A digital phase-domain phase-locked loop circuit comprising:
- a digitally-controlled oscillator (DCO);
- a gain element feeding the DCO and operational to compensate for DCO gain in response to a loop gain alpha multiplier signal;
- an oscillator phase accumulator operational to accumulate DCO generated clock edges;
- a reference phase accumulator operational to accumulate a frequency division ratio command and a modulating data signal and to generate an accumulated frequency control word (FCW) therefrom;
- a phase detector operational to compare the accumulated FCW and the accumulated DCO generated clock edges and generate a phase error in response thereto;
- a loop gain alpha multiplier element operational to generate the loop gain alpha multiplier signal in response to a filtered direct modulator output signal;
- and
- a direct modulator operational in response to the modulating data signal and the filtered phase error to generate the filtered direct modulator output signal.
5 more elements
A digital phase-domain phase-locked loop circuit comprising:
- a digitally-controlled oscillator (DCO);
- a gain element feeding the DCO and operational to compensate for DCO gain in response to a direct modulator output signal;
- an oscillator phase accumulator operational to accumulate DCO generated clock edges;
- a reference phase accumulator operational to accumulate a frequency division ratio command and a modulating data signal and to generate an accumulated frequency control word (FCW) therefrom;
- a phase detector operation to compare the accumulated FCW and the accumulated DCO generated clock edges and generate a phase error in response thereto;
- a loop gain alpha multiplier element operational to generate a loop gain alpha multiplier signal in response to the phase error;
- and
- a direct modulator operational in response to the modulating data signal and the alpha multiplier signal to generate the direct modulator output signal.
5 more elements
A phase-locked loop system comprising:
- a digitally-controlled oscillator responsive to an oscillator tuning word (OTW) to generate an oscillator clock;
- a direct modulator operational in response to a modulating data signal and a phase error to generate the OTW;
- and
- a phase-locked loop (PLL) operational in response to a channel selection signal and the modulating data signal to generate the phase error, the phase-locked loop (PLL) including a loop gain multiplier operational to generate a multiplier signal in response to the phase error.
1 more element
A phase-locked loop system comprising:
- a digitally-controlled oscillator responsive to an oscillator tuning word (OTW) to generate an oscillator clock, the digitally-controlled oscillator comprising a voltage controlled oscillator and a digital-to-analog converter operational to generate an oscillator tuning voltage in response to the OTW;
- a direct modulator operational in response to a modulating data signal and a phase error to generate the OTW;
- and
- a phase-locked loop (PLL) operational in response to a channel selection signal and the modulating data signal to generate the phase error, the phase-locked loop (PLL) including a loop gain multiplier operational to generate a multiplier signal in response to the phase error.
1 more element
A phase-locked loop system comprising:
- a digitally-controlled oscillator responsive to an oscillator tuning word (OTW) to generate an oscillator clock;
- a direct modulator operational in response to a modulating data signal and a phase error to generate the OTW, said direct modulator comprising a combinational element feeding the digitally controlled oscillator such that an oscillator gain can be compensated to substantially remove its effects on loop behavior;
- and
- a phase-locked loop (PLL) operational in response to a channel selection signal and the modulating data signal to generate the phase error, the phase-locked loop (PLL) including a loop gain multiplier operational to generate a multiplier signal in response to the phase error.
1 more element
A phase-locked loop system comprising:
- a digitally-controlled oscillator responsive to an oscillator tuning word (OTW) to generate an oscillator clock;
- a direct modulator operational in response to a modulating data signal and a phase error to generate the OTW;
- a phase-locked loop (PLL) operational in response to a channel selection signal and the modulating data signal to generate the filtered phase error, the phase-locked loop (PLL) including a loop gain multiplier operational to generate a multiplier signal in response to the phase error;
- and
- a direct modulation switch element operational to selectively attenuate a feed-forward path associated with the PLL.
2 more elements
A phase-locked loop system comprising:
- a digitally-controlled oscillator responsive to an oscillator timing word (OTW) to generate an oscillator clock;
- a direct modulator operational in response to a modulating data signal and a filtered phase error to generate the OTW;
- a phase-locked loop (PLL) operational in response to a channel selection signal and the modulating data signal to generate the filtered phase error;
- and
- a direct modulation switch element operational to selectively attenuate a feed-forward path associated with the PLL wherein a path through the direct modulator is defined by a transfer path gain between the modulation switch element and the digitally-controlled oscillator and wherein the transfer path gain is dependent upon a reference frequency fref and an estimated digitally-controlled oscillator gain {circumflex over (K)}DCO, is functionally defined as f ref K ^ DC0 .
2 more elements
A phase-locked loop system comprising:
- a digitally-controlled oscillator responsive to an oscillator tuning word (OTW) to generate an oscillator clock;
- a direct modulator operational in response to a modulating data signal and a phase error to generate the OTW;
- and
- a phase-locked loop (PLL) operational in response to a channel selection signal and the modulating data signal to generate the phase error, said PLL comprising a phase detector feeding filter, wherein the phase detector is responsive to the channel selection signal and the modulating data signal to generate said phase error, the phase-lkocked loop (PLL) including a loop gain multiplier operational to generate a multiplier signal in response to the phae error.
1 more element
A method of operating a digital phase-locked loop (PLL) system comprising the steps of:
- (a) providing a phase-locked loop including a digitally-controlled oscillator (DCO) having a gain KDCO, and a phase detector, wherein the DCO is responsive to an oscillator tuning word (OTW) to generate a DCO output clock having a frequency ƒv, and further wherein the phase detector is responsive to a channel selection signal, a modulating data signal and the output clock to generate a phase error;
- (b) providing a direct modulator operational in response to the phase error and the modulating data signal to generate the OTW;
- (c) observing an accumulated phase Δφ in the phase error in response to a given change Δx in the OTW;
- and
- (d) estimating the DCO gain {circumflex over (K)}DCO, defined by K ^ DC0 = Δ φ Δ x · f ref
- such that a DCO gain can be compensated to substantially remove its effects on loop behavior.
3 more elements
A method of operating a digital phase-locked loop (PLL) comprising the steps of:
- providing a phase-locked loop including a digitally-controlled oscillator (DCO) having a gain KDCO, and a phase detector wherein the DCO is responsive to an oscillator tuning word (OTW) to generate a DCO output clock having a frequency ƒv and further
- wherein the phase detector is responsive to a channel selection signal, a modulating data signal and the output clock to generate a phase error;
- providing a direct modulator oprational in response to the phase error and the modulating data signal to generate the OTW;
- observing an accumulated phase ΔØ in the phase error in response to a given change Δx in the OTW;
- and
- estimating the DCO gain such that a DCO gain can be compensated to substantially remove its effects on loop behavior.
3 more elements
Dependencies are inferred from the claim text.