US 6,809,399 B2Granted

Semiconductor integrated circuit device and process for manufacturing the same

AssigneesRenesas Technology Corp., Hitachi ULSI Systems Co., Ltd.

InventorsShuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu

Life of this patent

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Abstract

A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Claims10

Dependent claims

A semiconductor integrated circuit device, comprising:

a memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, and a capacitor element,
each of said first n-channel MISFET and said second n-channel MISFET having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
each of said first p-channel MISFET and said second p-channel MISFET having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate;
and
a first local wiring and a second local wiring formed on said semiconductor substrate and comprised of a different conductive layer from that of said gate electrodes of said n-channel and p-channel MISFETs, with an insulating film interposed therebetween,
each of said first local wiring and said second local wiring having a resistance lower than that of said gate electrodes of said n-channel and p-channel MISFETs,
said first local wiring being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, for forming a first storage node of said memory cell,
said second local wiring being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET, for forming a second storage node of said memory cell,
one capacitor electrode of said capacitor element being electrically connected to said first storage node and said first local wiring,
another capacitor electrode of said capacitor element being electrically connected to said second storage node and said second local wiring,
said one capacitor electrode of said capacitor element being formed over said another capacitor electrode of said capacitor element,
a dielectric film of said capacitor element being comprised of a silicon nitride film formed between said one capacitor electrode of said capacitor element and said another capacitor electrode of said capacitor element.

9 more elements

A semiconductor integrated circuit device, comprising:

a memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, and a capacitor element,
each of said first n-channel MISFET and said second n-channel MISFET having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
each of said first p-channel MISFET and said second p-channel MISFET having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate;
and
a first local wiring and a second local wiring formed on said semiconductor substrate and comprised of a different conductive layer from that of said gate electrodes of said n-channel and p-channel MISFETs, with an insulating film interposed therebetween,
each of said first local wiring and said second local wiring having a resistance lower than that of said gate electrodes of said n-channel and p-channel MISFETs,
said first local wiring being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, for forming a first storage node of said memory cell,
said second local wiring being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET, for forming a second storage node of said memory cell,
one capacitor electrode of said capacitor element being electrically connected to said first storage node and said first local wiring,
another capacitor electrode of said capacitor element being electrically connected to said second storage node and said second local wiring,
said one capacitor electrode of said capacitor element being superposed over said another capacitor electrode of said capacitor element.

8 more elements

A semiconductor integrated circuit device comprising:

a memory cell including a first n-channel MISFET, a second n-channel MISFET, a first p-channel MISFET, a second p-channel MISFET, and a capacitor element,
each of said first n-channel MISFET and said second n-channel MISFET having a gate electrode formed on a semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate,
each of said first p-channel MISFET and said second p-channel MISFET having a gate electrode formed on said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate;
and
a first local wiring and a second local wiring formed on said semiconductor substrate and comprised of a different conductive layer from that of said gate electrodes of said n-channel and p-channel MISFETs, with an insulating film interposed therebetween,
each of said first local wiring and said second local wiring having a resistance lower than that of said gate electrodes of said n-channel and p-channel MISFETs,
said first local wiring being electrically connected to said drain region of said first n-channel MISFET, said drain region of said first p-channel MISFET, said gate electrode of said second n-channel MISFET, and said gate electrode of said second p-channel MISFET, for forming a first storage node of said memory cell,
said second local wiring being electrically connected to said drain region of said second n-channel MISFET, said drain region of said second p-channel MISFET, said gate electrode of said first n-channel MISFET, and said gate electrode of said first p-channel MISFET, for forming a second storage node of said memory cell,
one capacitor electrode of said capacitor element being electrically connected to said first storage node and said first local wiring,
another capacitor electrode of said capacitor element being electrically connected to said second storage node and said second local wiring,
said one capacitor electrode of said capacitor element being formed over said another of capacitor electrode of said capacitor element.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/304,045Filed 26 Nov 2002 · continuation
Priority: JP 6-11492527 May 1994
Published: US 2003/0122159 A13 Jul 2003
Granted: 26 Oct 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 10/00
Static random access memory [sram] devices
G11C 11/4125
Using field-effect transistors only: cells incorporating circuit means for protecting against loss of information
H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 89/00
Aspects of integrated devices not covered by groups h10d84/00 - h10d88/00

Family

Application08/451,117Parent of this continuation · filed 25 May 1995
Application08/880,736Parent of this division · filed 23 Jun 1997
US 5,754,467 AParent of this continuation · filed 19 May 1998
Application09/334,266Parent of this division · filed 16 Jun 1999
US 5,946,565 AParent of this division · filed 31 Aug 1999
Application09/755,184Parent of this continuation · filed 8 Jan 2001
US 6,211,084 B1Parent of this division · filed 3 Apr 2001
US 6,548,885 B2Parent of this continuation · filed 15 Apr 2003
US 2003/0122159 A1Pre-grant publication · published 3 Jul 2003
Application09/755,184Parent of this division
Application08/880,736Parent of this continuation
US 2001/0019641 A1Published application
US 6,211,004 B1Related patent
US 6,809,399 B2This patent

From the US filing history. Foreign family members aren’t listed.