Performance of integrated circuit components via a multiple exposure technique

A set of masks with definitions created by reading at least a portion of an initial layout of an integrated device layer, identifying one or more target features within the initial layout, creating a first revised layout definition for a first mask, the first revised layout definition including the one or more target features and adjacent clear areas inside dark-field content, and creating a second revised layout definition for a second mask, the second revised layout definition including one or more dark features inside bright-field content, wherein the one or more dark features, when used in a multiple exposure fabrication process, will overlap the one or more target features.

An integrated device layer, created by exposing a photoresist applied on a wafer to a first mask created by a first layout definition and thereafter to a second mask created by a second layout definition, and processing the photoresist, wherein:

• the first layout definition comprises one or more target features from an initial layout of the integrated device layer and adjacent clear areas inside dark-field content;
• and
• the second layout definition comprises one or more dark features inside bright-field content, the one or more dark features overlapping the one or more target features when being used in a multiple exposure fabrication process.

A set of masks with definitions created by reading at least a portion of an initial layout of an integrated device layer, identifying two or more target features within the initial layout that are positioned at a distance from each other that is below a limit associated with an isolated pattern, creating a first revised layout definition for a first mask, the first revised layout definition including the two or more target features surrounded by clear areas inside dark-field content, and creating a second revised layout definition for a second mask, the second revised layout definition including one or more dark features inside bright-field content, wherein the one or more dark features, when used in a multiple exposure fabrication process, will overlap the two or more target features and at least a portion of the corresponding clear areas.

An integrated device layer, created by exposing a photoresist applied on a wafer to a first mask created by a first layout definition and thereafter to a second mask created by a second layout definition, and processing the photoresist, wherein:

• the first layout definition comprises two or more target features from an initial layout of the integrated device layer that are separated by a distance that is less than a limit associated with isolated patterns and are surrounded by clear areas inside dark-field content;
• and
• the second layout definition comprises one or more dark features inside bright-field content, the one or more dark features overlapping the two or more target features and at least a portion of the corresponding clear areas when being used in a multiple exposure fabrication process.

A computer-readable medium on which data is stored for defining a first and second mask for creating at least one target feature defined in an initial layout of an integrated circuit device with a multiple exposure fabrication, the medium including:

• data representing a first mask including a dark feature and clear areas adjoining the dark feature within a dark-field that correspond to the target feature in the initial layout;
• and
• data representing a second mask including a feature within a bright-field, wherein the feature of the second mask covers the dark feature and at least a portion of the clear areas adjoining the dark feature when used in a multiple exposure process.

A computer-readable medium of which data is stored for creating a first and second mask to create a layout of an integrated circuit device with a multiple exposure process, the medium containing:

• data representing dark features and adjacent clear areas within a dark-field that correspond to target features within the layout requiring fabrication with a multiple exposure process;
• and
• data representing dark features within a clear field that overlap the dark features and at least a portion of the adjacent clear areas corresponding to the target features and data representing dark features within the clear field that correspond to features in the layout of the integrated circuit that do not require fabrication with a multiple exposure process.