Systems and methods for performing clock gating checks

A system for perfonning a clock gating check on a logic cell comprising:

• means for determining a clock transition time of a clock signal input into the logic cell;
• means for determining a transition time of at least one gating signal input into the logic cell;
• means for calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell;
• and
• means for determining that the logic cell passes the clock gating check if the clock difference time is not negative;
• means for subtracting approximately half of a clock transition period from the clock difference time;
• and
• means for subtracting approximately half of a gating signal transition period from the clock difference time.

A computer readable storage medium containing program code for performing a clock gating check on a logic cell comprising:

• a first code segment configured to determine a clock transition time of a clock signal input into the logic cell;
• a second code segment configured to determine a transition time of at least one gating signal input into the logic cell;
• a third code segment configured to calculate a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell;
• and
• a fourth code segment configured to determine that the logic cell fails the clock gating check if the clock difference time is negative;
• wherein said third code segment is further configured to:
• subtract approximately half of a clock transition period from the clock difference time;
• and
• subtract approximately half of a gating signal transition period from the clock difference time.

A clock gating check system that performs clock gating check on a logic cell comprising:

• logic that determines a clock transition time of a clock signal input into the logic cell;
• logic that determines a transition time of at least one gating signal input into the logic cell;
• logic that calculates a clock difference time between the clock transition time and the transition time of the at least one gating signal input into the logic cell;
• and
• logic that determines the logic cell fails the clock gating check if the clock difference time is negative;
• logic that subtracts approximately half of a clock transition period from the clock difference time;
• and
• logic that subtracts approximately half of a gating signal transition period from the clock difference time.

A method for performing a clock gating check on a logic cell comprising the steps of:

• providing a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell;
• determining that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal;
• and
• determining that the logic cell passes the clock gating check responsive to the step of determining that there is no transition overlap.

A method for performing a clock gating check on a logic cell comprising the steps of:

• providing a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal to be input into the logic cell;
• determining that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal;
• determining that the logic cell passes the clock gating check responsive to the step of determining that there is no transition overlap;
• calculating a clock difference time between the clock transition time and the transition time of the at least one gating signal;
• subtracting approximately one-half of a clock transition period from the clock difference time;
• and
• subtracting approximately one-half of a gating signal transition period from the clock difference time.

A system for performing a clock gating check on a logic cell, the system comprising:

• memory having stored therein a timing database comprising clock signal and gating signal timing information, wherein the timing information includes information about a clock transition time of a clock signal to be input into the logic cell and a transition time of at least one gating signal input to be into the logic cell;
• and
• at least one processor that is programmed to determine that there is no transition overlap between the clock transition time and the transition time of the at least one gating signal;
• wherein the at least one processor is programmed to calculate a clock difference time between the clock transition time and the transition time of the at least one gating signal;
• and
• wherein the at least one processor is programmed to subtract approximately one-half of a clock transition period from the clock difference time, and to subtract approximately one-half of a gating signal transition period from the clock difference time.

A method for performing a clock gating check on a logic cell comprising the steps of:

• providing a clock transition value of a clock signal to be input into the logic cell and a transition value of at least one gating signal to be input into the logic cell;
• providing a value indicating a permissible level of overlap between the clock transition value and the transition value of the at least one gating signal;
• and
• determining that a transition overlap between the clock transition value and the transition value of the at least one gating signal does not exceed the permissible level of overlap.