Decoupling capacitance estimation and insertion flow for ASIC designs
AssigneeLSI Logic Corporation
InventorsLihui Cao, Prasad Subbarao, David Gradin, Maad Al-Dabagh, Weidan Li
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Abstract
A method for estimating decoupling capacitance during an ASIC design flow is disclosed. The method includes precharacterizing a set of power grid structures to model their respective noise behaviors, and storing the respective noise behaviors as noise factors in a table. During the ASIC design flow for a current design that includes at least one of the precharacterized power grid structures, the corresponding noise factor from the table is used to calculate decoupling capacitance for the current design.
Claims27
A method for estimating decoupling capacitance during a design flow, the method comprising the steps of:
- (a) performing a precharacterization stage independent of a particular design by,
- (i) precharacterizing a set of power grid structures to model their respective noise behaviors;
- (ii) storing the respective noise behaviors as noise factors in a table;
- and
- (b) performing a decoupling capacitance estimation stage during ASIC design flow for a current design that includes at least one of the power grid structures by,
- (i) using the corresponding noise factor from the table to calculate decoupling capacitance for the current design.
A method for estimating decoupling capacitance during a design flow, the method comprising the steps of:
- (i) modeling a set of power grid structures to obtain respective noise factors for each;
- (ii) storing the noise factors in a first table;
- (iii) characterizing a set of memory, and logic structures to obtain respective sets of peak current parameters;
- (iv) storing the peak current parameters in a second table;
- (v) for a design that includes any combination of the power, package, memory, and logic structures, looking up the corresponding noise factors and peak current parameters from the first and second tables;
- and
- (vi) using the noise factors and peak current parameters retrieved from the tables to calculate decoupling capacitance and a number of required decoupling capacitors for the design.
A computer readable medium containing program instructions for estimating decoupling capacitance during a design flow, the instructions for:
- (a) performing a precharacterization stage independent of a particular design by,
- (i) precharacterizing a set of power grid structures to model their respective noise behaviors;
- (ii) storing the respective noise behaviors as noise factors in a table;
- and
- (b) performing a decoupling capacitance estimation stage during ASIC design flow for a current design that includes at least one of the power grid structures by,
- (i) using the corresponding noise factor from the table to calculate decoupling capacitance for the current design.
Dependencies are inferred from the claim text.