System and method for time slicing deterministic patterns for reseeding in logic built-in self-test

A system for performing built-in self-test in a logic circuit comprising:

• an external controller for overall test flow control coupled to a circuit under test (CUT) having an LFSR coupled to a plurality of parallel channels coupled to a multiple input signature register (MISR), and a control counter;
• a first plurality of storage locations containing seed values;
• and;
• a second plurality of storage locations containing seed lifetime values, wherein each seed value has a respective seed lifetime value.

A computer readable medium containing executable instructions which, when executed in a processing system, causes the system to perform the steps for testing a circuit having an LFSR and, a plurality of parallel channels composed of channel segments, coupled to the LFSR, and a seed lifetime control counter, comprising:

• a) loading a seed into the LFSR;
• b) loading a seed lifetime into a control counter;
• c) shifting the LFSR per the seed lifetime to fill a channel segment with bit sequences from the LFSR;
• and,
• d) repeating a) through c) until the parallel channels have been filled with a test pattern, wherein at least two seed lifetimes have different values.