Split computer architecture to separate user and processor while retaining original user interface
AssigneeAvocent Corporation
InventorsRemigius G. Shatas, Robert R. Asprey, Christopher L. Thomas, Greg O'Bryant, Greg Luterman, Jeffrey E. Choun
Life of this patent
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Abstract
A network interface is described in which a single computer bus is split over a long distance into two or more inter-communicating buses. On one bus, processing and applications are provided and on the other remote bus, peripheral and local controllers are provided. The buses communicate through a series of: bridge, FPGA, FPGA and bridge. Between the FPGAs, a communication path provides long distance communication.
Claims19
A method of communicating from a first data bus to a second data bus, comprising:
- addressing interactive data from the first data bus to a first bridge;
- passing the interactive data from the first bridge to a first logic device and in said first logic device:
- a) buffering the interactive data in a first FIFO;
- b) outputting the interactive data from the first FIFO across a clock domain barrier;
- and
- c) continuing to store the interactive data after said step b);
- packeting the interactive data into packet data;
- delivering the packet data to a proximate portion of a long distance communication medium;
- receiving the packet data at a distal portion of the long distance communication medium;
- depacketing the packet data back into interactive data;
- passing the interactive data to a second logic device and in said second logic device:
- a) buffering the interactive data in a second FIFO;
- and
- b) outputting the interactive data from the second FIFO received across the clock domain barrier;
- receiving the interactive data from the second logic device at a second bridge;
- and
- addressing the interactive data from the second bridge to the second data bus.
A remote-distance communications interface between a processor and physically disassociated peripheral controllers, comprising:
- a first data bus onto which the processor communicates;
- a second data bus, physically disassociated from the first data bus, onto which the disassociated peripheral controllers communicate;
- a bus interface coupling the first and second data buses;
- and
- a clock domain barrier separating said first and second data buses;
- wherein the bus interface communicates first data bus data to the second data bus, and
- wherein the bus interface comprises:
- a first data bus interface circuit that couples the bus interface to the first data bus, the first data bus interface circuit comprising a first bridge;
- and
- a second data bus interface circuit that couples the bus interface to the second data bus, the second data bus interface circuit comprising a second bridge.
Dependencies are inferred from the claim text.