Apparatus for and method of in-band clock compensation

An in band clock compensation system for use in a synchronous data processing module, said module including a first in first out (FIFO) queue and adapted to receive an input data stream, said system comprising:

• means for periodically inserting a first number of clock sync symbols into said data stream;
• means for removing all but a second number of clock sync symbols from said input data stream;
• and
• symbol stuffing means operative to:
• insert a third number of clock sync symbols into said data stream if the level of said queue is below a lower threshold;
• insert a fourth number of clock sync symbols into said data stream if the level of said queue is above said lower threshold and below an upper threshold;
• insert a fifth number of clock sync symbols into said data stream if the level of said queue is above said upper threshold.

A method in band clock compensation for use in a synchronous data processing system, said system including a plurality of processing modules each including a first in first out (FIFO) queue and adapted to receive an input data stream, said method comprising the steps of:

• periodically inserting a first number of clock sync symbols into the data stream before being received by a first module;
• at each module, removing all but a second number of clock sync symbols from said input data stream;
• determining the level of said queue in said module;
• if said level is below a lower threshold, inserting a third number of clock sync symbols into said data stream;
• if said level is above said lower threshold and below an upper threshold, inserting a fourth number of clock sync symbols into said data stream;
• and
• if said level is above said upper threshold, inserting a fifth number of clock sync symbols into said data stream.

An in band clock compensation system for use in a communications device, comprising:

• a receive line card adapted to periodically insert a first number of clock sync symbols into a data stream output therefrom;
• and
• one or more switch cards, each switch card comprising a first first in first out (FIFO) queue and operative to:
• remove all but a second number of clock sync symbols from said data stream;
• and
• insert a third number of clock sync symbols into said data stream if the level of said first queue is below a lower threshold;
• insert a fourth number of clock sync symbols into said data stream if the level of said first queue is above said lower threshold and below an upper threshold;
• insert a fifth number of clock sync symbols into said data stream if the level of said first queue is above said upper threshold.

A clock compensation apparatus for use in a synchronous data processing module, comprising:

• an input buffer for receiving an input data stream wherein one or more clock sync symbols are periodically inserted therein;
• means for removing all but a second number of clock sync symbols from said input data stream;
• a first in first out (FIFO) queue adapted to receive said input data stream, said system means for inserting a first number of clock sync symbols into said data stream;
• data processing operative to process said input data stream;
• a clock compensation mechanism operative to:
• insert a first number of clock sync symbols into said data stream if the level of said queue is below a lower threshold;
• insert a second number of clock sync symbols into said data stream if the level of said queue is above said lower threshold and below an upper threshold;
• insert a third number of clock sync symbols into said data stream if the level of said queue is above said upper threshold;
• an output buffer for outputting the data stream output of said clock compensation mechanism.