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US 6,807,625 B1Granted
Method and apparatus for efficiently generating, storing, and consuming arithmetic flags between producing and consuming macroinstructions when emulating with microinstructions
AssigneeHewlett-Packard Development Company, L.P.
InventorsPatrick Knebel, Mark Gibson, Rohit Bhatia, Kevin David Safford
Life of this patent
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Abstract
An apparatus and method for efficiently generating arithmetic flags in a computer system. The system includes an eflags register to stored partially computed flags computed by an arithmetic logic unit. The stored partial flags are computed in one cycle. The stored flags are decoded by one of two consuming instructions, PRODF or TBIT, in a second cycle.
Claims21
A method for emulating the production and consumption of arithmetic flags in a single cycle comprising:
- partially emulating a flag producing macroinstruction that performs an arithmetic operation, wherein the partially emulating step comprises executing a sequence of one or more microinstructions that:
- generate an arithmetic result as specified by the macroinstruction;
- generate one or more partial arithmetic flags from the results of the generating an arithmetic result step;
- and
- store in an intermediate format the one or more partial arithmetic flags and one or more bits of extra information based on the type and size of the arithmetic operation, the intermediate format being arbitrarily defined to include as much computation towards final results as resources allow;
- passing the one or more partial arithmetic flags and one or more bits of extra information across the macroinstruction boundary signifying the completion of the flag producing macroinstruction;
- and
- emulating a flag consuming macroinstruction, wherein the emulating step comprises executing a sequence of one or more microinstructions that:
- generate one or more final flags from the one or more partial arithmetic flags and the one or more bits of extra information;
- and
- complete the emulation of the flag consuming macroinstruction using the one or more final flags.
8 more elements
A method for emulating the production of arithmetic flags and storage to memory in an architected format in a single cycle, comprising:
- partially emulating a flag producing macroinstruction that performs an arithmetic operation, wherein the partially emulating step comprises executing a sequence of one or more microinstructions that:
- generates an arithmetic result as specified by the macroinstruction;
- generates one or more partial arithmetic flags from the results of the generating an arithmetic result step;
- and
- stores in an intermediate format the one or more partial arithmetic flags and one or more bits of extra information based on the type and size of the arithmetic operation, the intermediate format being arbitrarily defined to include as much computation towards final results as resources allow;
- passing the one or more partial arithmetic flags and one or more bits of extra information across the macroinstruction boundary signifying the completion of the flag producing macroinstruction;
- and executing a sequence of microinstructions, wherein the execution:
- generates one or more final flags from the one or more partial arithmetic flags and the one or more bits of extra information;
- and
- stores the one or more final flags to a location in main memory in an architected format.
7 more elements
A method for emulating the production and consumption of flags in a single cycle comprising:
- partially emulating a flag producing macroinstruction that performs an operation, wherein the partially emulating step comprises executing a sequence of one or more microinstructions that:
- generates a result of the operation as specified by the macroinstruction;
- generates one or more partial flags from the results of the generating a result step;
- and
- stores in an intermediate format the one or more partial flags and one or more bits of extra information based on the type and size of the operation, the intermediate format being arbitrarily defined to include as much computation towards final results as resources allow;
- passing the one or more partial flags and one or more bits of extra information across the macroinstruction boundary signifying the completion of the flag producing macroinstruction;
- and
- emulating a flag consuming macroinstruction, wherein the emulating step comprises executing a sequence of one or microinstructions that:
- generates one or more final flags from the one or more partial flags and the one or more bits of extra information, wherein:
- if the flag producing macroinstruction is an explicit flag-writing operation, then the generating one or more final flags step comprises using a first block of hardware to decode the one or more partial flags, and
- if the flag producing macroinstruction is an implicit flag-writing operation, then the generating one or more final flags step comprises using a second block of hardware to decode the one or more partial flags;
- and
- completes the emulation of the flag consuming macroinstruction using the one or more final flags.
10 more elements
Dependencies are inferred from the claim text.