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US 6,807,622 B1Granted
Processor which overrides default operand size for implicit stack pointer references and near branches
AssigneeAdvanced Micro Devices, Inc.
InventorKevin J. McGrath
Life of this patent
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Abstract
A processor supports a mode in which the default operand size is 32 bits, but which supports operand size overrides to 64 bits. Furthermore, the default operand size may automatically be overridden to 64 bits for instructions having an implicit stack pointer reference and for near branch instructions. The overriding of the default operand size may occur without requiring an operand size override encoding in these instructions. In one embodiment, the instruction set specifying the instructions may be a variable byte length instruction set (e.g. x86), and the operand size override encoding may be a prefix byte which increases the instruction length.
Claims49
A processor comprising:
- a plurality of segment registers including a code segment register and a stack segment register;
- a circuit configured to generate an indication of a default operand size, wherein the circuit is configured to generate the default operand size responsive to a segment descriptor indicated by a segment selector stored in the code segment register, and wherein, in a first operating mode of a plurality of operating modes indicated at least in part by a content of the segment descriptor, each other one of the plurality of segment registers except for the code segment resister is ignored for providing segment data;
- and
- an execution core coupled to receive a first instruction, wherein the execution core is configured, in the first operating mode, to override the default operand size with a second operand size responsive to the first instruction having an implicit stack pointer reference.
1 more element
A method comprising:
- generating a default operand size for instructions responsive to a segment descriptor indicated by a segment selector stored in a code segment register, wherein the code segment register is one of a plurality of segment registers that also includes a stack segment register, and wherein the segment descriptor further indicates an operating mode, and wherein each other one of the plurality of segment registers except for the code segment register is ignored in the operating mode for providing segment data;
- and
- overriding the default operand size with a second operand size for a first instruction, in the operating mode, responsive to the first instruction having an implicit stack pointer reference.
A processor comprising:
- a plurality of segment registers including a code segment resister and a stack segment register;
- a circuit configured to generate an indication of a default operand size, wherein the circuit is configured to generate the default operand size responsive to a segment descriptor indicated by a segment selector stored in the code segment register, and wherein, in a first operating mode of a plurality of operating modes indicated at least in part by a content of the segment descriptor, each other one of the plurality of segment registers except for the code segment register is ignored for providing segment data;
- and
- an execution core coupled to receive a near branch instruction, wherein the execution core is configured to override the default operand size with a second operand size responsive to the near branch instruction in the first operating mode.
1 more element
A method comprising:
- generating a default operand size for instructions responsive to a segment descriptor indicated by a segment selector stored in a code segment register, wherein the code segment register is one of a plurality of segment registers that also includes a stack segment register, and wherein the segment descriptor further indicates an operating mode, and wherein each other one of the plurality of segment registers except for the code segment register is ignored in the operating mode for providing segment data;
- and
- overriding the default operand size, in the operating mode, with a second operand size for a near branch instruction.
An apparatus comprising:
- a plurality of storage locations corresponding to a plurality of segment registers, wherein the plurality of segment registers include a code segment register and a stack segment register;
- and
- a processor configured to generate an indication of a default operand size, wherein the processor is configured to generate the default operand size responsive to a segment descriptor indicated by a segment selector stored in a storage location of the plurality of storage locations that corresponds to the code segment register, and wherein, in a first operating mode of a plurality of operating modes indicated at least in part by a content of the segment descriptor, each other one of the plurality of segment registers except for the code segment register is ignored for providing segment data, and wherein, in response to a first instruction having an implicit stack reference and the first operating mode, the processor is configured to override the default operand size with a second operand size.
An apparatus comprising:
- a plurality of storage locations corresponding to a plurality of segment registers, wherein the plurality of segment registers include a code segment register and a stack segment register;
- and
- a processor configured to generate an indication of a default operand size, wherein the processor is configured to generate the default operand size responsive to a segment descriptor indicated by a segment selector stored in one of the plurality of storage locations corresponding to the code segment register, and wherein, in a first operating mode of a plurality of operating modes indicated at least in part by a content of the segment descriptor, each other one of the plurality of segment registers except for the code segment register is ignored for providing segment data, and wherein the processor is configured to override the default operand size with a second operand size responsive to a near branch instruction in the first operating mode.
Dependencies are inferred from the claim text.