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AssigneeTelefonaktiebolaget LM Ericsson
InventorsJoachim Strömbergson, Magnus Carlsson, Jonas Vasell
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A pipelined microprocessor for processing instructions includes at least one pipeline. The pipeline includes and instruction fetching functional stage, an instruction decoding functional stage, an execution functional stage comprising a number of execution units and a commit functional stage. The commit functional stage includes or is associated with a reorder buffer. Detecting means are provided for detecting instruction irregularities. When an instruction irregularity is detected, an irregularity indication and a flush instruction are generated. The irregularity indication is used to initiate a flush made whereas the flush instruction, when received in a stage or unit set in flush mode, resets the flush mode in said stage/unit.
A pipelined microprocessor for processing instructions, comprising at least one pipeline comprising an instruction fetching functional stage, an instruction decoding functional stage, an execution functional stage comprising a number of execution units, and a commit functional stage comprising or being associated with a reorder buffer, wherein the microprocessor further includes detecting means for detecting instruction irregularities, such that when an instruction irregularity is detected, an irregularity indication and a flush instruction are generated, and the irregularity indication is used to initiate a flush mode, whereas the flush instruction, when received in a functional stage or unit set in flush mode, resets the flush mode in said functional stage/unit.
A method of processing instructions in a pipelined microprocessor comprising at least one pipeline comprising an instruction fetching functional stage, an instruction decoding functional stage, an execution functional stage and a commit functional stage, the method comprising the steps of:
Dependencies are inferred from the claim text.