Back to results
US 6,807,618 B1Granted
Address translation
AssigneeEMC Corporation
InventorJohn Kemeny
Life of this patent
Estimating the term…
Abstract
The description includes techniques of data storage address translation. The techniques can include receiving a first address in a first address space, traversing a trie based on the first address, and determining a second address based on the traversal.
Claims13
A method comprising:
- representing a plurality of memory addresses associated with at least one storage device as a plurality of hierarchical branches in a trie data structure;
- receiving a request for data stored at a particular one of the memory addresses of the at least one storage device;
- traversing at least some of the hierarchical branches in the trie data structure using different portions of the particular one of the memory addresses storing the requested data;
- identifying a memory address associated with a cache memory based on the traversal, the identified cache memory address being stored in a leaf of the trie data structure;
- and
- transmitting data stored at the identified cache memory address in response to the request.
3 more elements
A data storage system, comprising:
- (a) at least one storage device;
- (b) a cache memory;
- (c) instructions for causing a processor to:
- (1) represent a plurality of memory addresses associated with the at least one storage device as a plurality of hierarchical branches in a trie data structure;
- (2) receive a request for data stored at a particular one of the memory addresses of the at least one storage device;
- (3) traverse at least some of the hierarchical branches in the trie data structure using different portions of the particular one of the memory addresses storing the requested data;
- (4) identify a memory address associated with the cache memory based on the traversal, the identified cache memory address being stored in a leaf of the trie data structure;
- and
- (5) transmit data stored at the identified cache memory address in response to the request.
6 more elements
A computer program product, disposed on a computer readable medium, the computer program product including instructions for causing a processor to:
- represent a plurality of memory addresses associated with at least one storage device as a plurality of hierarchical branches in a trie data structure;
- receive a request for data stored at a particular one of the memory addresses of the at least one storage device;
- traverse at least some of the hierarchical branches in the trie data structure using different portions of the particular one of the memory addresses storing the requested data;
- identify a memory address associated with a cache memory based on the traversal, the identified cache memory address being stored in a leaf of the trie data structure;
- and
- transmit data stored at the identified cache memory address in response to the request.
3 more elements
Dependencies are inferred from the claim text.