Method and apparatus for using smart memories in computing
OwnerShine C. Chunginventor
Life of this patent
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Abstract
A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.
Claims22
A smart memory computing system to process data in parallel, said smart memory system comprising:
- a central processing unit;
- a main memory unit that provides data storage for said central processing unit;
- a smart memory unit to not only store data for said central processing unit but also to process data therein;
- a massive data storage that provides storage for a superset of data stored in said main memory system and in said smart memory system;
- and
- a trigger mechanism for said central processing unit to initiate processing of a processing batch by said smart memory unit.
A smart memory computing system to process data in parallel, said smart memory system comprising:
- a central processing unit;
- a main memory unit that provides data storage for said central processing unit;
- a smart memory unit to not only store data for said central processing unit but also to process data therein;
- a massive data storage that provides storage for a superset of data stored in said main memory system and in said smart memory system;
- and
- a stall mechanism for stalling execution by at least part of said smart memory unit.
A smart memory computing system to process data in parallel, said smart memory system comprising:
- a central processing unit;
- a main memory unit that provides data storage for said central processing unit;
- a smart memory unit to not only store data for said central processing unit but also to process data therein, wherein said smart memory unit comprises a first smart memory integrated circuit and a second smart memory integrated circuit;
- a massive data storage that provide storage for a superset of data stored in said main memory system and in said smart memory system;
- and
- a bus operatively connecting said first and second smart memory integrated circuits to at least one of said main memory unit and said central processing unit.
A smart memory computing system to process data in parallel, said smart memory system comprising:
- a central processing unit;
- a main memory unit that provides data storage for said central processing unit;
- a smart memory unit to not only store data for said central processing unit but also to process data therein;
- a massive data storage that provides storage for a superset of data stored in said main memory system and in said smart memory system;
- means for said central processing unit to interact with said smart memory system;
- and
- a trigger mechanism for said central processing unit to initiate processing of a processing batch by said smart memory unit.
Dependencies are inferred from the claim text.