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US 6,807,609 B1Granted
Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system
AssigneeHewlett-Packard Development Company, L.P.
InventorsPaul J. Lemmon, Raj Ramanujan
Life of this patent
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Abstract
A computer system is adapted to transfer write data from a central processing unit to one of a plurality of memory modules in a memory array by transferring a block of write data to a memory control logic device. The memory control logic device transfers the block of data in a plurality of data bursts interspaced by a preselected number of bus cycles. During the interspaced preselected number of bus cycles, the memory control logic device sends pending read commands to an available memory module thereby overlapping read and write operations on the memory bus, thus, lowering memory read latency.
Claims59
A method for interleaving a read operation and a write operation on a bus having a bus cycle time in a computer system including the bus and a first device, the method comprising the steps of:
- a) operating the first device to transmit a portion of a write data block on the bus during a first period, the first period including at least one bus cycle time;
- b) operating the first device to pause for a preselected number of bus cycle times;
- c) operating the first device to transmit a read command on the bus during the preselected number of bus cycle times pause;
- and
- d) operating the first device to transmit a further portion of the write data block on the bus during a second period, the second period including at least one bus cycle time.
2 more elements
A method for interleaving a read operation and a write operation on a bus having a bus cycle time in a computer system which comprises the bus, a memory control logic device and a plurality of memory modules, the memory control logic device coupled to the plurality of memory modules by the bus, comprising the steps of:
- a) operating the memory control logic device to transmit a portion of a write data block on the bus from the memory control logic device during a first period, the first period including at least one bus cycle time, to a first one of the plurality of memory modules;
- b) operating the memory control logic device to pause for a preselected number of bus cycle times;
- c) operating the memory control logic device to transmit a read command on the bus from the memory control logic device to a second one of the plurality of memory modules during the preselected number of bus cycle times pause;
- and
- d) operating the memory control logic device to transmit a further portion of the write data block on the bus from the memory control logic device during a second period, the second period including at least one bus cycle time, to the first one of the plurality of memory modules.
2 more elements
A method for transmitting data to a memory module in a memory system that communicates over a bus having a bus cycle time, where the bus cycle time is less than the memory latency of the memory module, the bus is coupled to the memory module, the method comprising the steps of:
- (a) operating the memory module to receive a portion of a write data block on the bus;
- (b) operating the memory module to not receive a further portion of the write data block for a preselected number of bus cycle times;
- (c) operating the memory module to store the portion of the write data block received by the memory module;
- and
- (d) repeating steps (a), (b) and (c) until the write data block has been stored by the memory module.
2 more elements
A method for minimizing buffering requirements on a memory module in a memory system that communicates over a bus having a bus cycle time, where the bus cycle time is less than the memory latency of the memory module, the memory module is coupled to the bus, the memory module comprises a buffer and a random access memory, the method comprising the steps of:
- (a) operating the memory module to receive a portion of a write data block on the bus to the memory module;
- (b) operating the memory module to capture the portion of the write data block in the buffer;
- (c) operating the memory module to not receive a further portion of the write data for a preselected number of bus cycle times;
- (d) operating the memory module to transfer the portion of the write data block from the buffer to the random access memory;
- and
- (e) repeating the steps (a), (b), (c) and (d) until the entire write data block has been stored by the memory module in the random access memory.
3 more elements
A method for transmitting data to a memory module in a computer system which comprises the memory module, a memory control logic device having storage means, and a bus having a bus cycle time, the bus is coupled to the memory module, and the memory control logic device, the bus cycle time is less than the memory latency of the memory module, the method comprising the steps of:
- (a) operating the memory control logic device to transmit a portion of a write data block from the memory control logic device over the bus to the memory module;
- (b) operating the memory control logic device to pause a preselected number of bus cycle times before transmitting a further portion of the write data block;
- (c) operating the memory module to store the portion of the write data block received by the memory module;
- and
- (d) repeating steps (a), (b) and (c) until the entire write data block has been stored by the memory module.
2 more elements
The method according to 20 wherein the step of operating the memory module to store the portion of the write data received by the memory module further comprises a step of operating the memory module to transfer each one of the plurality of subportions of the write data block from the buffer to the random access memory.
A method for transmitting data to a plurality of memory modules in a memory system and interleaving a read operation with a write operation on a bus in the memory system, the bus, having a bus cycle time, is coupled to the plurality of memory modules, comprising the steps of:
- (a) operating a first one of the plurality of memory modules to receive a portion of a write data block on the bus;
- (b) operating the first one of the plurality of memory modules to not receive a further portion of the write data block for a preselected number of bus cycle times;
- (c) operating the first one of the plurality of memory modules to store the portion of the write data block received by the first one of the plurality of memory modules;
- (d) operating a second one of the plurality of memory modules to receive any pending read commands on the bus during the preselected number of bus cycle times pause;
- and
- (e) repeating steps (a), (b), (c) and (d) until the write data block has been stored by the first one of the plurality of memory modules.
3 more elements
A method for transmitting data to a plurality of memory modules in a computer system and interleaving a read operation with a write operation on a second bus in the computer system, the second bus having a second bus cycle time, the computer system comprises a central processing unit, a memory control logic device having storage means, a first bus, the plurality of memory modules and the second bus, the first bus intercoupling the central processing unit and the memory control logic device, the second bus intercoupling the memory control logic device and the plurality of memory modules, comprising the steps of:
- (a) operating the central processing unit to transmit a write command and a write data block over the first bus from the central processing unit to the memory control logic device;
- (b) operating the memory control logic device to transmit a portion of the write data block over the second bus from the memory control logic device to a first one of the plurality of memory modules;
- (c) operating the memory control logic device to pause a preselected number of second bus cycle times;
- (d) operating the first one of the plurality of the memory modules to store the portion of the write data block received by the first one of the plurality of memory modules;
- (e) operating the memory control logic device to transmit any pending read commands on the second bus during the preselected number of second bus cycle times pause from the memory control logic device to a second one of the plurality of memory modules;
- and
- (f) repeating steps (b), (c), (d) and (e) until the write data block has been stored by the first one of the plurality of memory modules.
4 more elements
A computer system comprising:
- (a) a bus having a bus cycle time;
- (b) a memory control logic device coupled to the bus, the memory control logic device comprising:
- (i) a write buffer having a plurality of locations, each having an address,
- (ii) a multiplexer having a plurality of data inputs, control inputs and an output, the control inputs select one of the plurality of multiplexer inputs to be coupled to the output of the multiplexer, and
- (iii) a control logic section;
- (c) the plurality of multiplexer inputs coupled to outputs of the write buffer, each one of the outputs corresponds to a subportion of a write data block, the multiplexer transmits one of the plurality of subportions of the write data block stored in the write buffer on the bus during at least one bus cycle time;
- (d) the control logic section having outputs coupled to the control inputs of the multiplexer, the control logic section deselects the output of the multiplexer for a preselected number of bus cycle times;
- (e) the control logic section further transmits any pending read commands on the bus during the preselected number of bus cycle times the output of the multiplexer is deselected.
5 more elements
A computer system comprising:
- (a) a bus having a bus cycle time;
- (b) a memory control logic device coupled to the bus, the memory control logic device comprising:
- (i) a write buffer having inputs, outputs, and a plurality of locations, each one of the plurality of locations having an address, and
- (ii) a multiplexer having a plurality of data inputs, control inputs and an output, the control inputs select one of the plurality of multiplexer inputs to be coupled to the output of the multiplexer, and
- (iii) a control logic section;
- (c) the plurality of multiplexer inputs coupled to the outputs of the write buffer, each one of the outputs of the write buffer corresponds to a subportion of a write data block, the multiplexer transmits one of a plurality of subportions of the write data block stored in the write buffer on the bus during at least one bus cycle time;
- (d) the control logic section having outputs coupled to the control inputs of the multiplexer, the control logic section deselects the output of the multiplexer for a preselected number of bus cycle times;
- (e) the control logic section further transmits any pending read commands during the preselected number of bus cycle times the output of the multiplexer is deselected;
- and
- (f) a memory module coupled to the bus, the memory module comprising:
- (i) a buffer having inputs and outputs, the inputs of the buffer being coupled to the bus, the buffer captures the subportions of the write data block transmitted on the bus, and
- (ii) a random access memory device having inputs and outputs coupled to the buffer outputs, the device stores the subportions of the write data block captured in the buffer.
9 more elements
A computer system comprising:
- (a) a first bus;
- (b) a central processing unit coupled to the first bus, the central processing unit transmits a write command and a write data block on the first bus;
- (c) a second bus having a second bus cycle time;
- (d) a memory control logic device coupled to the first bus and the second bus, receives the write command and write data block from the first bus, the memory control logic device comprising:
- (i) a write buffer having inputs, outputs, and a plurality of locations, each having an address, and
- (ii) a multiplexer having a plurality of data inputs, control inputs and an output, the control inputs select one of the plurality of multiplexer inputs to be coupled to the output of the multiplexer, and
- (iii) a control logic section;
- (e) the plurality of multiplexer inputs coupled to the outputs of the write buffer, each one of the outputs corresponds to a subportion of a write data block stored in the write buffer, the multiplexer transmits a plurality of subportions of the write data block stored in the write buffer on the second bus during at least one second bus cycle time;
- (f) the control logic section having outputs coupled to the control inputs of the multiplexer, the control logic section deselects the output of the multiplexer for a preselected number of second bus cycle times;
- (g) the control logic section further transmits a read command over the second bus during the preselected number of second bus cycle times the output of the multiplexer is deselected.
7 more elements
A computer system comprising:
- (a) a first bus;
- (b) a central processing unit coupled to the first bus, the central processing unit transmits a write command and a write data block on the first bus;
- (c) a second bus having a second bus cycle time;
- (d) a memory control logic device coupled to the first bus and the second bus, the memory control logic device receives the write command and write data block from the first bus, the memory control logic device comprising:
- (i) a write buffer having outputs and a plurality of locations, each of the plurality of locations having an address, and
- (ii) a multiplexer having a plurality of data inputs, control inputs and an output, the control inputs select one of the plurality of multiplexer inputs to be coupled to the output of the multiplexer, and
- (iii) a control logic section;
- (e) the plurality of multiplexer inputs coupled to the outputs of the write buffer, each one of the outputs corresponds to a subportion of a write data block stored in the write buffer, the multiplexer transmits a plurality of subportions of the write data block stored in the write buffer on the second bus during at least one second bus cycle time;
- (f) the control logic section having outputs coupled to the control inputs of the multiplexer, the control logic section deselects the output of the multiplexer for a preselected number of second bus cycle times;
- (g) the control logic section further transmits a read command on the second bus during the preselected number of second bus cycle times the output of the multiplexer is deselected;
- and
- (h) a memory module coupled to the bus, the memory module comprising:
- (i) a buffer having inputs and outputs, the inputs of the buffer being coupled to the bus, the buffer captures the subportions of the write data block transmitted on the bus, and
- (ii) a random access memory device having inputs and outputs coupled to the buffer outputs, the device stores the subportions of the write data block captured in the buffer.
11 more elements
A computer system comprising:
- (a) a bus having a bus cycle time;
- (b) a memory control logic device coupled to the bus, the memory control logic device comprising a buffer having a plurality of locations, data inputs, control inputs, and data outputs, having a write data block stored in the plurality of locations, and buffer control logic, the outputs of the buffer being coupled to the bus and outputs of the buffer control logic being coupled to the control inputs of the buffer;
- (c) the buffer control logic providing outputs to the buffer causing the buffer to transmit the write data block on the bus in a plurality of data bursts interspaced by a preselected number of bus cycle times.
A computer system comprising:
- (a) a bus having a bus cycle time;
- (b) a memory control logic device coupled to the bus, the memory control logic device comprising a buffer, the buffer having a plurality of locations, data inputs, control inputs and outputs, the memory control logic device also having a write data block stored in the plurality of locations, and buffer control logic, the outputs of the buffer being coupled to the bus and outputs of the buffer control logic being coupled to the control inputs of the buffer;
- (c) the buffer control logic providing outputs to the buffer causing the buffer to transmit the write data block on the bus in a plurality of data bursts interspaced by a preselected number of bus cycle times;
- (d) a memory module coupled to the bus, comprising:
- (i) a buffer having inputs and outputs, the inputs being coupled to the bus, the buffer captures the plurality of data bursts from the bus, and
- (ii) a random access memory device having inputs and outputs coupled to the outputs of the buffer, the device stores the plurality of data bursts captured by the buffer.
3 more elements
A computer system comprising:
- (a) a first bus;
- (b) a central processing unit coupled to the bus transmits a write command and a write data block on the first bus;
- (c) a second bus having a second bus cycle time;
- (d) a memory control logic device coupled to the first bus and the second bus, the memory control logic device comprising a buffer having data inputs, control inputs and outputs, and buffer control logic having inputs and outputs, the data inputs of the buffer being coupled to the first bus and outputs of the buffer being coupled to the second bus, an output of the buffer control logic being coupled to control inputs of the buffer;
- (e) the buffer receives the write data block from the first bus;
- (f) the buffer control logic providing outputs to the buffer causing the buffer to transmit the write data block on the second bus in a plurality of data bursts interspaced by a preselected number of second bus cycle times.
3 more elements
A computer system comprising:
- (a) a first bus;
- (b) a central processing unit coupled to the bus, the central processing unit transmits a write command and a write data block on the first bus;
- (c) a second bus having a second bus cycle time;
- (d) a memory control logic device coupled to the first bus and the second bus, the memory control logic device comprising a buffer having data inputs, control inputs and outputs, and buffer control logic having inputs and outputs, the data inputs of the buffer being coupled to the first bus and outputs of the buffer being coupled to the second bus, an output of the buffer control logic being coupled to control inputs of the buffer;
- (e) the buffer receives the write data block from the first bus;
- (f) the buffer control logic providing outputs to the buffer causing the buffer to transmit the write data block on the second bus in a plurality of data bursts interspaced by a preselected number of second bus cycle times;
- (g) a memory module coupled to the bus, comprising:
- (i) a buffer having inputs and outputs, the inputs being coupled to the bus, the buffer captures the plurality of data bursts from the bus, and
- (ii) a random access memory device having inputs and outputs coupled to the outputs of the buffer, the device stores the plurality of data bursts captured by the buffer.
6 more elements
A memory module comprising:
- (a) a random access memory device having inputs and outputs;
- (b) a control logic device having inputs and outputs, the inputs coupled to a bus having a bus cycle time, the outputs being coupled to the random access memory device;
- (c) the control logic device providing outputs to the random access memory device causing the random access memory device to store a block of data transmitted on the bus in a plurality of data bursts interspaced by a preselected number of bus cycle times.
A memory module comprising:
- (a) a bus having a cycle time;
- (b) a random access memory device having data inputs and outputs and control inputs;
- (c) a first state machine coupled to the bus in such a manner for receiving data;
- (d) a bidirectional logic device having two sets of inputs and outputs and control inputs, intercoupling the first state machine and the random access memory device, having inputs of a first set of the inputs and outputs coupled to the first state machine, having outputs of the first set of inputs and outputs coupled to the bus in such a manner as to store data received from the first state machine and the random access memory device and a second set of inputs and outputs coupled to the random access memory device in such a manner as to store data from the random access memory device;
- (e) a control logic device having outputs coupled to the control inputs of the random access memory device and the bidirectional logic device, the control logic device controlling the bidirectional logic device to store a block of data transmitted in a plurality of data bursts interspaced by a preselected number of bus cycle times;
- (f) the control logic device providing outputs to the random access memory device causing the random access memory device to store the plurality of data bursts in the random access memory device.
3 more elements
A memory module comprising:
- (a) a bus having a cycle time;
- (b) a random access memory device having data inputs and outputs and control inputs;
- (c) a first state machine coupled to the bus to receive data;
- (d) a bidirectional logic device having two sets of inputs, two sets of outputs, and control inputs, the bidirectional logic device intercoupling the first state machine and the random access memory device, having inputs of a first set of the inputs and outputs coupled to the first state machine, having outputs of the first set of inputs and outputs coupled to the bus to store data received from the first state machine and the random access memory device and a second set of inputs and outputs coupled to the random access memory device to store data from the random access memory device;
- (e) a control logic device having outputs coupled to the control inputs of the random access memory device and the bidirectional logic device, the control logic device controlling the bidirectional logic device to store a block of data transmitted in a plurality of data bursts interspaced by a preselected number of bus cycle times;
- (f) the control logic device providing outputs to the random access memory device causing the random access memory device to store the plurality of data bursts in the random access memory device.
3 more elements
Dependencies are inferred from the claim text.