System and method for input/output module virtualization and memory interleaving using cell map

A method of accessing a plurality of memories in an interleaved manner and a plurality of input/output modules using a contiguous logical address space, the method comprising:

• providing at least one map table, the at least one map table including a plurality of entries, each entry including an entry type identifier and a plurality of entry items, each entry item including a module identifier, each entry being one of a memory type entry and an input/output type entry;
• receiving a first logical address, the first logical address including a plurality of address bits;
• identifying an entry in the at least one map table based on a first set of the address bits;
• determining a type of the identified entry based on the entry type identifier of the identified entry;
• identifying an entry item in the identified entry based on a second set of the address bits if the entry type identifier indicates an input/output type entry;
• identifying an entry item in the identified entry based on a third set of the address bits if the entry type identifier indicates a memory type entry;
• and
• accessing a module identified by the module identifier of the identified entry item.