System and method for mapping bus addresses to memory locations utilizing access keys and checksums

A computer system, comprising:

• memory systems, each of said memory systems having memory locations for storing data;
• at least one processor configured to transmit requests to write data values to said memory locations in said memory systems, said requests including bus addresses;
• a first mapper configured to map consecutive ones of said bus addresses to a plurality of memory addresses, respectively, each of said memory addresses identifying a memory location in a different one of said memory systems, said first mapper further configured to associate each of said memory addresses with a different one of a plurality of checksum identifiers, each of said checksum identifiers identifying a different one of said memory systems, said first mapper having a plurality of entries, each of said entries identifying a different block of contiguous memory locations in said memory systems, said first mapper configured to map said consecutive ones of said bus addresses to said plurality of memory addresses by mapping said consecutive ones of said bus addresses to different ones of said entries;
• and
• a second mapper having a plurality of different access keys, said second mapper configured to map, to said plurality of different access keys, a plurality of different bus addresses that are mapped to a same one of said entries by said first mapper, wherein each of said different bus addresses is mapped to only a respective one of said access keys,
• wherein each of said checksum identifiers that is associated with a particular one of said memory addresses identifies one of said memory systems storing a checksum value that is based on a data value stored at a memory location identified by said particular one memory address.

A computer system, comprising:

• memory systems, each of said memory systems having memory locations for storing data;
• at least one processor configured to transmit requests to write data values to said memory locations in said memory systems, said requests including bus addresses;
• and
• a mapping system configured to map consecutive ones of said bus addresses to a plurality of memory addresses, respectively, each of said memory addresses identifying a memory location in a different one of said memory systems, said mapping system further configured to associate each of said memory addresses with a different one of a plurality of checksum identifiers, each of said checksum identifiers identifying a different one of said memory systems,
• wherein each of said checksum identifiers that is associated with a particular one of said memory addresses identifies one of said memory systems storing a checksum value that is based on a data value stored at a memory location identified by said particular one memory address, and wherein said mapping system includes:
• a first mapper having a plurality of entries, each of said entries including a memory system identifier identifying one of said memory systems and a memory unit offset corresponding to one of said memory locations in said memory system identified by said memory system identifier included in said each entry, said first mapper configured to utilize said entries to map each of a plurality of said bus addresses to different ones of said memory addresses;
• and
• a second mapper having a plurality of entries, each of said entries including one of a plurality of access keys, each of said access keys uniquely identifyng a respective protection domain, said second mapper configured to map each of said bus addresses to a respective one of said access keys, wherein said second mapper mas different ones of said access keys to a plurality of different bus addresses that are mapped to a same one of said first mapper entries such that each of said different ones of said access s keys is mapped to less than all of said plurality of different bus addresses by said second mapper,
• wherein said mapping system is configured to transmit one of said access keys mapped from one of said bus addresses along with one of said memory address mapped from said one bus address.

A processing system, comprising:

• memory systems, each of said memory systems having memory and a memory controller for storing data to said memory and retrieving data from said memory;
• means for transmitting requests to write data values, said requests including consecutive bus addresses;
• means for mapping said consecutive bus addresses into memory addresses such that each of said memory addresses identifies a memory location in a different one of said memory systems, said mapping means configured to select checksum system identifiers in response to said requests to write data values such that said checksum system identifiers identify each of said plurality of said memory systems, said mapping means having a plurality of entries, each of said entries identifyng a different block of contiguous memory locations in said memory systems, said mapping means configured to map said consecutive bus addresses to different ones of said entries;
• means for mapping, to a plurality of different access keys, a plurality of different bus addresses that are mapped to same a one of said entries such that each of said plurality of different access keys is mapped to less than all of said plurality of different bus addresses;
• and
• means for updating checksum values stored in each of said plurality of said memory systems based on said checksum system identifiers.

A method, comprising the steps of:

• providing memory systems, each of said memory systems having memory and a memory controller for storing and retrieving data;
• receiving requests to write data values, said requests including consecutive bus addresses;
• mapping said consecutive bus addresses into memory addresses, said mapping including the step of mapping said consecutive bus addresses to different entries of a mapper, each of said entries identifying a block of contiguous memory locations within a respective one of said memory systems;
• mapping, to a plurality of different access keys, a plurality of different bus addresses that are mapped to a same one of said entries such that each of said plurality of different access keys is mapped to less than all of said plurality of different bus addresses;
• identifyng each of said memory systems based on said memory addresses;
• selecting checksum system identifiers in response to said requests to write data values;
• identifying each of said plurality of said memory systems based on said checksum system identifiers;
• and
• updating checksum values stored in each of said plurality of said memory systems based on said checksum identifiers.

A method, comprising the steps of:

• providing memory systems, each of said memory systems having memory and a memory controller for storing and retrieving data;
• receiving requests to write data values, said requests including consecutive bus addresses;
• mapping said consecutive bus addresses into memory address, said mapping including the step of mapping said consecutive bus addresses to different entries of a mapper, each of said entries identifying a block of contiguous memory locations within a respective one of said memory systems;
• mapping, to a plurality of different access keys, a plurality of different bus addresses that are mapped to a same one of said entries such that each of said plurality of different bus addresses is mapped to only a respective one of said plurality of different access keys;
• interleaving said memory addresses across each of said memory systems;
• storing said data values based on said memory addresses.

A computer system, comprising:

• memory systems;
• a first mapper having a plurality of entries, said first mapper configured to map a consecutive set of bus addresses to memory addresses that are interleaved across said memory systems, said first mapper configured to map said bus addresses to checksum identifiers that are interleaved across said memory systems, said first mapper configured to map each of said bus addresses to a different one of said entries, each of said entries identifying a block of contiguous memory locations in a different one of said memory systems;
• and
• a second mapper having a plurality of access keys, said second mapper configured to map said bus addresses to said access keys,
• wherein said first mapper is configured to map a plurality of different bus addresses to a same one of said entries and said second mapper is configured to map each of said plurality of different bus addresses to a different one of said access keys such that at least one of said access keys is mapped to a respective one but less than all of said plurality of different bus addresses.