Integrated circuit device having double data rate capability
AssigneeRambus Inc.
InventorsMichael Farmwald, Mark Horowitz
Life of this patent
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Abstract
A synchronous integrated circuit device including a clock receiver to receive an external clock signal and a plurality of output drivers to output data. A first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal. A second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal. In addition, the integrated circuit device includes a delay locked loop, coupled to the plurality of output drivers and the clock receiver, to synchronize the output of the first and second portions of the data with the external clock signal.
Claims40
A synchronous integrated circuit memory device including an array of memory cells, wherein the memory device comprises:
- a clock receiver to receive an external clock signal;
- a plurality of output drivers to output data, wherein:
- a first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal;
- and
- a second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal;
- and
- a delay locked loop, coupled to the plurality of output drivers and the clock receiver, to synchronize the output of the first and second portions of the data with the external clock signal.
An integrated circuit device that operates synchronously with respect to a first external clock signal, wherein the integrated circuit device comprises:
- a clock synchronization circuit, wherein the clock synchronization circuit includes:
- a first delay line to generate a first internal clock signal, wherein the first internal clock signal has a delay with respect to the first external clock signal;
- and
- a comparator to compare the first internal clock signal with the first external clock signal, wherein the delay of the first internal clock signal is controlled based on the comparison between the first internal clock signal and the first external clock signal;
- and
- a plurality of output drivers to output data, wherein:
- a first portion of the data is output synchronously with respect to a rising edge transition of the first external clock signal;
- and
- a second portion of the data is output synchronously with respect to a falling edge transition of the first external clock signal;
- and
- a plurality of multiplexers, coupled to the plurality of output drivers and the clock synchronization circuit, to provide the data to the plurality of output drivers in response to transitions of the first internal clock signal.
A method of operation of an integrated circuit device wherein the method of operation of the integrated circuit device comprises:
- receiving a first external clock signal;
- generating a first internal clock signal to synchronize output of data with the first external clock signal, wherein the first internal clock signal has a delay time with respect to the first external clock signal;
- comparing the first internal clock signal with the first external clock signal, wherein the delay time of the first internal clock signal is controlled based on the comparison between the first internal:
- clock signal and the first external clock signal;
- outputting a first portion of the data synchronously with respect to a rising edge transition of the first external clock signal;
- and
- outputting a second portion of the data synchronously with respect to a falling edge transition of the first external clock signal.
An integrated circuit memory device having a memory array which includes a plurality of memory cells, wherein the memory device comprises:
- a clock receiver to receive an external clock signal;
- a plurality of input receivers to sample an operation code synchronously with respect to the external clock signal, wherein the operation code specifies a read operation;
- an output driver to output data in response to the operation code wherein:
- a first portion of the data is output synchronously with respect to a rising edge transition of the external clock signal;
- and
- a second portion of the data is output synchronously with respect to a falling edge transition of the external clock signal;
- and
- a delay locked loop, coupled to the output driver and the clock receiver, to synchronize the output of the first and second portions of the data with the external clock signal.
Dependencies are inferred from the claim text.