Disconnecting a device on a cache line boundary in response to a write command
AssigneeHewlett-Packard Development Company, L.P.
InventorsJeff M. Carlson, Ryan A. Callison
Life of this patent
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AssigneeHewlett-Packard Development Company, L.P.
InventorsJeff M. Carlson, Ryan A. Callison
Estimating the term…
Efficient bus operations is provided by maintaining alignment with cache line boundaries in response to a write command. A write buffer in a bridge device receives data from any one of a multiple number of bus interfaces. Write buffer management is utilized to monitor on a continuous basis the amount of free space available in the write buffer. When the data in the write buffer approaches the capacity of the write buffer, the system prepares for a potential disconnect of the write initiating device from the bridge device. Data alignment with cache line boundaries is maintained upon disconnect by adjusting the available free space in the write buffer to equal a multiple of a cache line amount of data. The write initiating device is disconnected when the data in the write buffer equals a write buffer full status.
A method for processing write commands from a device in a computer system, comprising the steps of:
A computer bridge device for performing computer write operations between multiple systems, comprising:
A computer system for performing computer write operations, comprising:
A method for performing computer write operations, the method comprising the steps of:
Dependencies are inferred from the claim text.