Increased computer peripheral throughput by using data available withholding
AssigneeInternational Business Machines Corporation
InventorsThomas B. Berg, Adrian C. Moga, Dale A. Beyer
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AssigneeInternational Business Machines Corporation
InventorsThomas B. Berg, Adrian C. Moga, Dale A. Beyer
Estimating the term…
A method and apparatus for a mutiprocessor system to simultaneously process multiple data write command issued from one or more peripheral component interface (PCI) devices by controlling and limiting notification of invalidated address information issued by one memory controller managing one group of multiprocessors in a plurality of mutiprocessor groups. The method and apparatus permits a multiprocessor system to almost completely process a subsequently issued write command from a PCI device or other type of computer peripheral device before a previous write command has been completely processed by the system. The disclosure is particularly applicable to multiprocessor computer systems which utilize non-uniform memory access (NUMA).
A method for controlling sequencing of data writes from peripheral devices in a multiprocessor computer system having a plurality of memory systems and a plurality of processor groups operatively interconnected to each other, the method comprising:
A computer system comprising:
Dependencies are inferred from the claim text.