Method and apparatus for parallel carry chains

A computer readable medium having stored thereon information for use by a semiconductor design tool, comprising:

• a description of parallel carry chain structures, said parallel carry chain structures to perform a function, each of said carry chain structures comprising a series of logical structures, at least one of said logical structures within each of said carry chain structures having an input node, output node and carry node, said input node to provide an input term of said function, said output node to provide an output term of said function, said carry node to provide a carry value to a following logical structure in the carry chain to which the carry node belongs, wherein any output term output node does not reside downstream from both:
• signal lines within a first carry chain structure;
• and,
• signal lines within a second carry chain structure.

A method, comprising:

• a) presenting input terms of a function to parallel carry chain structures;
• b) executing each of said parallel carry chain structures in parallel to provide output terms of said function, where, in generating any output term of said function, terms generated by a first carry chain structure and terms generated by a second carry chain structure are not both sent to circuitry from which said output term is generated;
• and,
• c) receiving the output terms of said function from said parallel carry chain structures.

A method for designing a circuit to perform a function, said function to provide an output comprising output values in response to an input comprising input values, said method comprising:

• designing said circuit to have parallel carry chains that together perform said function, said parallel-carry chains comprising:
• (1) a first carry chain comprising a first logical structure that is preceded by a first preceding logical structure and that is followed by a first following logical structure, said first logical structure comprising:
• (i) a first input value input node to receive a first of said input values;
• (ii) a first carry term input node coupled to a carry term output node of said first preceding logical structure;
• (iii) a first output value output node to provide a first of said output values, said first output value output node not residing downstream from both a node within said first carry chain and a node within a second carry chain;
• (iv) a first carry term output node coupled to a carry term input node of said first following logical structure;
• and,
• (2) said second carry chain comprising a second logical structure that is preceded by a second preceding logical structure and that is followed by a second following logical structure, said second logical structure comprising:
• (i) a second input value input node to receive a second of said input values;
• (ii) a second carry term input node coupled to a carry term output node of said second preceding logical structure;
• (iii) a second output value output node to provide a second of said output values, said second output value output node not residing downstream from both a node within said first carry chain and a node within said second carry chain;
• (iv) a second carry term output node coupled to a carry term input node of said second following logical structure.

A machine readable medium containing instructions which when executed by a processing core cause a method to be performed for designing a circuit to perform a function, said function to provide an output comprising output values in response to an input comprising input values, said method comprising:

• designing said circuit to have parallel carry chains that together perform said function, said parallel carry chains comprising:
• (1) a first carry chain comprising a first logical structure that is preceded by a first preceding logical structure and that is followed by a first following logical structure, said first logical structure comprising:
• (i) a first input value input node to receive a first of said input values;
• (ii) a first carry term input node coupled to a carry term output node of said first preceding logical structure;
• (iii) a first output value output node to provide a first of said output values, said first output value output node not residing downstream from both a node within said first carry chain and a node within a second carry chain;
• (iv) a first carry term output node coupled to a carry term input node of said first following logical structure;
• and,
• (2) said second carry chain comprising a second logical structure that is preceded by a second preceding logical structure and that is followed by a second following logical structure, said second logical structure comprising:
• (i) a second input value input node to receive a second of said input values;
• (ii) a second carry term input node coupled to a carry term output node of said second preceding logical structure;
• (iii) a second output value output node to provide a second of said output values, said second output value output node not residing downstream from both a node within said first carry chain and a node within said second carry chain;
• (iv) a second carry term output node coupled to a carry term input node of said second following logical structure.

A machine readable medium containing instructions which when executed by a processing core cause a method to be performed, said method comprising:

• designing a semiconductor chip to perform the following operations:
• present input terms of a function to parallel carry chain structures;
• execute each of said parallel carry chain structures in parallel to provide output terms of said function, where, in generating any output term of said function, terms generated by a first carry chain structure and terms generated by a second carry chain structure are not both sent to circuitry from which said output term is generated;
• and,
• receive the output terms of said function from said parallel carry chain structures.