Digital true random number generator circuit
AssigneeSafeNet, Inc.
InventorRobert Vincent Michel Oerlemans
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AssigneeSafeNet, Inc.
InventorRobert Vincent Michel Oerlemans
Estimating the term…
A digital true random number generator circuit, comprising a linear feedback shift register having an input and an output, a system clock having a system clock frequency value for driving the shift register, and a plurality of free running oscillators operatively connected to the input of the shift register. The oscillators and the system clock having different oscillation frequency values, the greatest common divisor of which having the value one, thereby avoiding locking of the oscillators and the system clock.
A digital true random number generator circuit, comprising:
A digital true random number generator circuit, comprising:
A digital true random number generator circuit, comprising:
An Application Specific Integrated Circuit (ASIC) comprising:
An encryption device, comprising:
A transactions terminal, comprising:
Dependencies are inferred from the claim text.
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Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords: generation of secret information…
Random or pseudo-random number generators: random number generators, i.e. based on natural stochastic processes
Pseudo-random number generators: using finite field arithmetic, e.g. using a linear feedback shift register
Digital communication
Term ended 19 Nov 2022 (estimated)
1. Field of the Invention
The invention relates, in generals to circuits and techniques for generating random numbers, and in particular to digital semiconductor circuits for generating true random numbers.
2. Discussion of the Background
The present invention will now be described with reference to the accompanying drawings, wherein:
FIG. 1 discloses schematically an embodiment of a true random number generating circuit according to the invention;
FIG. 2 discloses schematically a specific embodiment of a linear feedback shift register for use in the true random number generator circuit according to the invention; and
FIG. 1 is a logic block diagram of an embodiment of a digital true random number generator circuit according to the invention. It incorporates a Linear Feedback Shift Register (LFSR) 4 having an input 4a, and an output 4b. LFSR's are known in practice to those skilled in the art and do not need to be further elucidated here.
In order to avoid the above described problem of “locking” of a driving oscillator and a system clock or counter 3, in accordance with the present invention, a plurality of free running oscillators 10, 20, 30 operatively connects to the input 2a of the LFSR 4. The oscillators have oscillation frequency values which differ among each other and of the system clock frequency value in a manner such that their greatest divisor is of the magnitude one.
In the embodiment of FIG. 1, for illustration purposes, three free running oscillators 10, 20, 30 are shown. However, those skilled in the art will appreciate that other numbers of oscillation devices may be used for the purpose of the present invention. In the embodiment shown, each free running oscillator 10, 20, 30 is constructed as a ring oscillator having a plurality of cascade connected inverter circuits 101-109, 201-207, 301-305 and furthermore having an output 10out, 20out, 30out, respectively.