US 6,807,552 B2 · Programmable non-integer fractional divider

Abstract

A non-integer fractional divider is disclosed. According to the present invention, the non-integer fractional divider comprises means for dividing a reference clock signal having a period ‘P’ by a non-integer ratio ‘K’. In a preferred embodiment, the divider comprises means for receiving a plurality ‘N’ of clock signals issued from the reference clock signal and wherein each clock signal is equally phase shifted by a ‘P/N’ delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality ‘N’ of clock signals. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio ‘K’. The selected clock signals are combined into combining means to generate a clock signal being phase shifted by the non-integer part of the non-integer ratio. Then, dividing means are coupled to the combining means for dividing the shifted clock signal by the integer part of the non-integer ratio.

Claims11

Dependent claims

A non-integer fractional divider (200) for dividing a reference clock signal ‘Fvco’ of period ‘P’ by a non-integer ratio ‘K’, the non-integer ratio being decomposed into an integer part ‘I’ and a non-integer part ‘X’, the non-integer fractional divider comprising:

first and second receiving means (202, 203) for respectively receiving an identical plurality ‘N’ of clock signals ‘Fvco—0 to Fvco_(N−1)’, each clock signal having a period of ‘P’ and being equally phase shifted by a ‘P/N’ delay one over the other and wherein the first clock signal ‘Fvco—0’ being in phase with the reference clock signal;
means (201) coupled to the first and second receiving means (202, 203) for selecting a first clock signal ‘PHI1’ from the first receiving means and a second clock signal ‘PHI2’ from the second receiving means;
means (205) for detecting the end of a (I−i)th period, wherein ‘i’ is a predetermined value;
means (204) coupled to the first and second receiving means (202, 203) and to the detection means (205) for combining said first and second selected clock signals (PHI1, PHI2) to generate a clock signal ‘Clock’ being phase shifted by the non-integer part value ‘X’ of the non-integer ratio;
and
means (205) coupled to the combining means (204) for dividing the shifted clock signal by the integer part ‘I’ of the non-integer ratio.

3 more elements

Dependencies are inferred from the claim text.

Programmable non-integer fractional divider

Life of this patent

Programmable non-integer fractional divider

Life of this patent

Abstract

Claims11