System and method for simulation of an integrated circuit design using a hierarchical input netlist and divisions along hierarchical boundaries thereof

A computer implemented method of simulating an integrated circuit design comprising the steps of:

• a) accessing an input netlist describing said integrated circuit design, said input netlist organized in a hierarchical fashion of cells and comprising connectivity information that describes connections between said cells;
• b) in response to an event, using said connectivity information to determine a group of leaf cells of said netlist that are effected by said event;
• c) of said group of leaf cells, dividing said group into stages based on hierarchical boundaries as defined in said netlist;
• d) transforming each of said stages into a separate Thevenin equivalent circuit model;
• e) using said Thevenin equivalent circuit models to compute cut node voltages of said stages and recording, in computer memory, said cut node voltages into a flat node voltage data structure;
• and
• f) repeating said steps b)-e) for multiple events.

A computer system comprising a processor coupled to bus and a memory coupled to said bus, wherein said memory contains instructions that when executed implement a method of simulating an integrated circuit design comprising the steps of:

• a) accessing an input netlist describing said integrated circuit design, said input netlist organized in a hierarchical fashion;
• b) in response to an event, determining a group of leaf cells of said netlist that are effected by said event;
• c) of said group of leaf cells, dividing said group into stages based on hierarchical boundaries as defined in said netlist;
• d) transforming each of said stages into a separate Thevenin equivalent circuit model, where appropriate;
• e) using said circuit models to compute cut node voltages of said stages and recording, in computer memory, said cut node voltages;
• and
• f) repeating said steps b)-e) for multiple events.