Circuit with interconnect test unit
AssigneeKoninklijke Philips Electronics N.V.
InventorsFranciscus G. M. De Jong, Mathias N. M. Muris, Robertus M. W. Raaijmakers, Guillaume E. A. Lousberg
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Abstract
An electronic circuit comprises a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects. A main unit implements a normal mode function of the electronic circuit. A test unit tests the interconnects. The electronic circuit has a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit. In the test mode the test unit is operable as a low complexity memory via the I/O nodes.
Claims9
An electronic circuit comprising:
- a plurality of input/output (I/O) nodes for connecting the electronic circuit to a further electronic circuit via interconnects,
- a main unit for implementing a normal mode function of the electronic circuit,
- and a test unit for testing the interconnects,
- the electronic circuit having a normal mode in which the I/O nodes are logically connected to the main unit and a test mode in which the I/O nodes are logically connected to the test unit,
- wherein the test unit comprises at least one combinatorial circuit implementing at least one of an XNOR function and an XOR function with at least two function inputs and a function output, the function inputs being connected to particular I/O nodes arranged to operate as input nodes of the test circuit and the function output being connected to a particular I/O node arranged to operate as output node of the test circuit.
Dependencies are inferred from the claim text.