Digital key telephone set and digital key telephone system
AssigneeKabushiki Kaisha Toshiba
InventorsToshiaki Takahashi, Toshiaki Tanaka, Takeshi Horiuchi
Life of this patent
Estimating the term…
Loading patent…
AssigneeKabushiki Kaisha Toshiba
InventorsToshiaki Takahashi, Toshiaki Tanaka, Takeshi Horiuchi
Estimating the term…
A clock generating circuit generates a clock of a rate corresponding to a Dch rate in response to a specification from the exterior. A counting circuit detects completion of reception of one frame by counting the clock number up to “11” at timing at which a start bit detecting circuit detects a start bit in a serial signal. An S/P converting circuit fetches a serial Dch signal bit by bit in synchronism with the clock, outputs the latest fetched 10 bits in a parallel form and latches eight bits of a real data portion among the output data into a latch circuit at the time when reception of one frame is completed. In parallel with the above operation, a parity calculating circuit and flag/interruption generating circuit set various flags and generate a reception completion interruption.
A digital key telephone set used as a key telephone set in a digital key telephone system which transmits a serial signal of n-bit frame structure, wherein n is a desired integral number of frame structure bits, including real data of m bits, wherein m is a desired integral number of real data bits, and preset additional bits including a start bit arranged in the head portion of the real data, from a key telephone unit to the key telephone set via a data channel, and fetches the real data among the serial signal by a controller of the terminal comprising:
A digital key telephone system comprising:
Dependencies are inferred from the claim text.